Honored Contributor
Honored ContributorIt has been quite a long time since I worked with this CAN controller, so I don't remember everything exactly.
Anyway, I try to recollect here some information. .wb_adr_i({2'b0, av_address[7:2]}) As you correctly pointed out, this is because Avalon is 32bit wide but it uses byte addressing. In a perfect world I've used the CAN controller with byte accesses (i.e. IORD_8DIRECT,IOWR_8DIRECT). Unfortunately Avalon fabric generates 4 8bit reads even with IORD_8DIRECT, because it requires a 32bit complete access to be performed: this is generally invisible to the application, since only the requested byte is returned by IORD_8DIRECT, but it makes a mess with devices involving fifo register which automatically pop data at every read access, and this CAN controller is one of them. That's why I remapped CAN register in order to access them as if they were 32bit wide. Please note that you must feed register addresses with multiple of 4, and discard higher 24 bits: data = IORD(OC_CAN_VERILOG_WRAP_0_BASE, reg*4) & 0xFF; IOWR(OC_CAN_VERILOG_WRAP_0_BASE, reg*4, data); The CAN controller works. I had some problems with FIFOs because of what I said above, but then it worked fine. I suggest you use 24 or 40MHz for CAN clock; IIRC with 10MHz you can't achieve all standard CAN baudrates
