Arria 10 IOPLL not locking when reconfiguring

Hi all,

I'm currently trying to reconfigure an IOPLL with the Reconfiguration IP-Core by accessing the registers of the Core.
The PLL has been configured to run with an 80 MHz input clock and 240 MHz output clock and locks.
The goal is to reconfigure the output to 80 MHz.
The sequence in doing so is the following:

1. Take parameters for reconfiguration from QSYS
2. Write M Register (0x90)
3. Write N Register (0xA0)
[3.1] Write 0 to address 0
4. Write C Registers (0xC0 and further)
[4.1] Write 0 to address 0 after each C Register change
5. Write Charge Pump (0x20) register
6. Write Loop Filter (0x40) register
7. Write 0 to address 0

Steps in brackets are optional. It didn't make a difference executing these steps or not doing them.

I'm currently observing the PLL not being able to lock at all (configured the IOPLL reconfiguration core with parameter WAIT_LOCKED = 0 to not hang my watchdog timer).
The output clock, when configured to 80 MHz jitters in between 70 and 80 MHz.
The input clock is stable 80 MHz. Simulaton of the whole system works as expected.
Reading back the written registers provides the exact values I've written.
I'm currently using Quartus Prime 20.1.1 Standard edition

Are there any bugs to be aware of and is there a solution to make the reconfiguration work? Many thanks for your help.