Forum Discussion
New ContributorArria 10 IOPLL not locking when reconfiguring
Hi @Ash_R_Intel ,
I just found, that I made an programming error and didn't configure the Loop Filter correctly. PLL is now locking. Many thanks for your patience and help.
Regular ContributorHi,
I am guessing that you are following AN 728.
You need not write 0 to address 0 after every write command. It is required at the end of the steps. This is not so problem creating step though.
It is important that you refer the Design Considerations mentioned on page 13.
Are you applying reset to the PLL? Is the design meeting the timing?
Regards.
New ContributorHi @Ash_R_Intel ,
I am following AN 728 and applying the avalon reset of the IOPLL after reconfiguration (asserting for 1 ms and waiting for 1 ms until evaluating lock).
Also I write 0 to address 0 after each command now.
Lock goes high for 722 clock cycles (measured with signaltap, 100 MHz -> 7.22 us) before going low again.
Timing is met for 240 MHz output clock and for 240 MHz the PLL locks without trouble (without reconfiguration). After reconfiguration with the same values that the PLL is initially configured with results in a loss of lock. The PLL is configured in direct mode. Changing this to normal or source-snychronous didn't change the behaviour either.
Many thanks for your help
- CHebl
Hi @Ash_R_Intel ,
I just found, that I made an programming error and didn't configure the Loop Filter correctly. PLL is now locking. Many thanks for your patience and help.
