Ash_R_Altera
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Re: Arria 10 Transceiver rx_cal_busy always HIGH for 24s after programming
Hi, I am referring to the following section of the Arria 10 transceiver PHY UG, https://docs.altera.com/r/docs/683617/21.1/arria-10-transceiver-phy-user-guide/power-up-calibration As per this, the power-up calibration has a sequence and RX PMA channel calibration almost comes at the end of it. Eventually the rx_cal_busy de-assertion will depends upon the whether the previous blocks i.e. ATX PLL and fPLL calibration are completed or not and whether the PCIe hard IP is enabled or not. If the PLLs are taking long, check the input reference clocks to it. Regards1View0likes0CommentsRe: Fitter Error with Clock Switchover Enabled in Altera PLL (Normal Mode)
Hi, Thanks for the design. I am able to reproduce the issue. Till now I could figure out that the issue is mainly due to the location which you are trying to use. If I disable the pin constraints and let the tool allocate it, is goes through the compilation. With this first thing that I would like to check with you is whether the input clock pin constraints are hard requirement for you or there is a flexibility to move to some other pins. Let me know please. Regards9Views0likes0CommentsRe: Agilex 3 VCCLSENSE and GNDSENSE
Hi, First thing is that whether the regulator that you choose is from a recommended list or not. Refer to https://docs.altera.com/r/docs/853726/current/pcb-design-guidelines-agilextm-3-fpgas-and-socs/fpga-core-fabric-vcc-voltage-regulator-selection Secondly, the VCCLSENSE and GNDSENSE are recommended to be a must connected pins for VCC core. These pins compensates for the DC IR drop associated with the PCB and device package from the VCC power. Altera strongly recommends to follow the guidelines provided for a smooth operation of the device. Any design outside the recommendations will not be supported. It will be at user risk. Regards, Altera support10Views0likes0CommentsRe: Global Clock & Regional clock inputs in Agilex M FPGA
Hi, Are you referring to the Agilex™ 7 FPGA M-Series Development Kit - HBM2e Edition (3x F-Tile & 1x R-Tile)? If so, it is a generic dev kit. Clocks of different frequencies drive different reference clocks and there sources are also different. It just provides flexibility to the user to choose a clock as they need. For example, tile 13A, refclk 4 (pin DJ14) is driven by CLK_390_625MHZ_2P, 390.625MHz clock. The source of it is SI5518 IC. At the same time the refclk 5 is driven by a 156.25MHz clock at pin DE14, source SI5394. Note that both SI5518 and SI5394 can also be modified to drive any other frequency using the clock controller tool. Depending on your application requirement you may choose either of the clock. An example scenario could be: quad 2 channels require 390.625MHz refclk let's say, so you choose refclk 4. At the same time, quad 3 channels may require 156.25MHz refclk, so you choose refclk 5. Regards5Views0likes0CommentsRe: Global Clock & Regional clock inputs in Agilex M FPGA
Hi, The F-tile transceiver channels are grouped in quads i.e. 4 channels in a group. Not all the reference clocks reach each of the FGT and FHT channel. You need not necessarily drive multiple reference clocks. Drive one of the global clocks that reach all the FGT channels i.e. either of Refclk 2, 3, 4 and 5 if all the channels you use can share the same frequency. Similarly FHT quad has its own refclk network. Kindly refer to the Reference Clock Network section of the F-tile Architecture user guide: https://docs.altera.com/r/docs/683872/26.1/f-tile-architecture-and-pma-and-fec-direct-phy-ip-user-guide/reference-clock-network Regards10Views0likes2Comments