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Ash_R_Altera
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Re: Tranceiver Enhanced PCS Basic mode questions
Hi, In the Cyclone 10 GX Enhanced PCS, the TX side has no built-in lock indicator because the transmitter does not perform word alignment. TX link health is confirmed by the far-end receiver: the remote device's rx_enh_blk_lock (or its equivalent) signals that your TX data stream has been correctly aligned at the other end. To surface this status locally, implement a feedback path in your FPGA logic that brings the remote RX lock signal back to your local TX domain. Regards2Views0likes1CommentRe: Unable to Generate Valid PAM4 Eye Diagram and BER Measurements on Stratix 10 SI E-Tile Native PHY
Hi, I suspect that probably the design is not properly configured to enable the TTK. Please refer the section 10.3 and make sure that the E-tile IP has correct settings enabled. https://docs.altera.com/r/docs/683723/current/e-tile-transceiver-phy-user-guide/modifying-the-design-to-enable-e-tile-transceiver-debug The latest version of the Quartus is 26.1. Recommend you to choose the latest one. For the design example, unfortunately there is none for PAM4 native PHY IP. Regards7Views0likes0CommentsRe: Agilex 5 Reset Sequencer - Design Assitant reports IPC-40038 violation
Hi, I am confused here a bit. Yes, PCS and PMA can reside in the same bank. But, as you have different banks 4C and 1C on right and left side respectively, there should be two reset sequencer IPs in your design. Each IPs pma_cu_clk port should connect to the PHY IP as shown in the diagram. Is that so in your design? Regards18Views0likes0CommentsRe: EP4CE22F 256 net length report not found
Hi BrianSune_Froum , I can't comment on the pricing side. You may check with local sales for that. On the netlength report side, the Cyclone IVE and Cyclone III share the same netlength reports, hence it is not published separately. Uploading the required netlength report file, for your reference. Regards17Views0likes3CommentsRe: Unable to Generate Valid PAM4 Eye Diagram and BER Measurements on Stratix 10 SI E-Tile Native PHY
Hi, Here are my recommendations: Step 1 — Upgrade Quartus Prime Pro (Critical) Quartus 18.1 is 8 years old. PAM4 E-Tile support has received extensive fixes since then. Recommend upgrading to at least Quartus 24.x (or latest). Many PAM4 adaptation, eye viewer, and toolkit fixes were delivered in 19.x–24.x releases. Step 2 — Use Proper PRBS Pattern for PAM4 The user-defined pattern does NOT exercise all 4 PAM4 voltage levels. This alone can cause "eye could not be detected." Use PRBS31Q (quaternary/PAM4-aware PRBS) from the Transceiver Toolkit's built-in pattern generator, not a custom pattern. This ensures all 4 symbol levels (0, 1, 2, 3) are properly exercised. Step 3 — Signal Integrity Check (SMA Cable) A 50 cm Pasternack PE3CA1035 SMA cable may have excessive insertion loss at 25.5 GHz (PAM4 Nyquist for 51 Gbps). Recommend: Use the shortest possible cable (< 15 cm) or a calibrated test fixture Alternatively, test with serial internal loopback (SILB) first to eliminate the cable as a variable Step 4 — Adaptation Sequence Run continuous adaptation (not one-time) for PAM4. The adaptation FSM needs to converge VGA/AGC, CTLE, DFE, and IQ timing for all 3 PAM4 eyes. After enabling continuous adaptation, wait for it to fully converge (observe stable CTLE/DFE tap values in Toolkit) before running Eye Viewer. Step 5 — TX Pre-emphasis / FIR Settings For a short SMA loopback, start with: Pre-tap = 0, Main tap = max (e.g., 55), Post-tap = 0 Adjust only if needed after confirming basic link with SILB Step 6 — Eye Viewer Configuration Ensure Eye Viewer is set to PAM4 mode (measures top, middle, and bottom eyes) Let the tool accumulate sufficient bits at each BER point (~10⁸ bits minimum at 51 Gbps before starting eye scan) Verify CDR lock-to-data is asserted before running Eye Viewer Step 7 — Verify lock status registers Before running Eye Viewer, confirm: rx_is_lockedtodata = 1 and rx_pll_locked = 1 If CDR is locked to reference (not data), the eye measurement will fail Recommended Debug Sequence (Short form for response) First: Try internal serial loopback with PRBS31Q → confirms transceiver PMA works If SILB passes: try external loopback with shortest cable available If short cable passes: troubleshoot with original 50 cm cable (likely too lossy) Regards0Views1like2CommentsRe: A3C* BSDL updates available?
Hi, I got a response back on the internal ticket that I raised. Team has generated the models internally and will be publishing them soon, in couple of weeks. Please watch out the page in a week or so. Thanks for your patience till then. Regards3Views0likes0CommentsRe: Agilex 5 Reset Sequencer - Design Assitant reports IPC-40038 violation
Hi, As I understand, this Warning is related to port o_pma_cu_clk of the Reset Sequencer IP. Please check if your connection is as per the documentation recommendation. The pma_cu_clk must be connected to your IPs. Please review your code once and let us know if you find something. Regards18Views0likes1Comment