Ash_R_Intel
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Re: Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered
Hi, I got a chance to discuss this topic with my colleagues. The recommendation is to follow the datasheet specifications. Read the footnotes also. https://docs.altera.com/r/docs/683301/current/agilextm-7-fpgas-and-socs-device-data-sheet-f-series-and-i-series/f-tile-transceiver-performance-specifications If you notice, there are recommendations on AC-coupling of the pins. The footnote 97 suggests that the FGT lines can be driven in unpowered state as well, provided the voltage are within the specified limits. Hope this helps. Regards12Views1like2CommentsRe: Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered
Hi, Specifically for the PCIe application, the F-tile supports the Hot Plug feature. Refer to the following documentation: https://docs.altera.com/r/docs/683140/25.3/f-tile-avalon-streaming-ip-for-pci-express-user-guide/hot-plug I think this is what you were looking for. Regards38Views1like4CommentsRe: Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX)
Yes, you understood it right. As 20G can be achieved only by GXT channels and for the clocking at that speed ATX pll is the preferred choice. Refer section 3.1 PLLs of the same document. Regards51Views1like4Comments