Ash_R_Intel
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Re: Agilex5での未使用GTS トランシーババンクのパワーダウンにつきまして
Hi, I am referring to following page: 2.2.3.1. Unused PMA Not Planned for Use in the Future For B23A package of A5E043, as 1C and 1B are on the same side, if both the banks are unused, you can still power both of them down (footnote 14 on the above link). Bank 4C can also be powered down, if it is completely unused. Hope this clarifies. Regards74Views0likes0CommentsRe: Critical Warnings Related to Unused Transceiver Channels in Quartus Prime Pro 20.4
Hi, The PRESERVE_UNUSED_XCVR_CHANNEL option should be used if you intend to use the XCVR channels in future. It is required to prevent the channels from degrading over the time. If you do not intend to use the XCVR channels at all in future, then follow the pin connection guidelines as mentioned in the following page: https://www.intel.com/content/www/us/en/docs/programmable/683814/current/transceiver-pins.html Regards120Views0likes0CommentsRe: onnecting the F-Tile Reference and System PLL Clock IP out_coreclk_#i port to an IOPLL FPGA IP
Hi, Could you verify if the port out_systempll_synthlock_i from F-tile system PLL IP gets asserted or not? You could use this port ANDed with your system level reset to generate overall reset to the IOPLL. Is the input clock to the system PLL always available and at the correct frequency? I don't see any problem is generating a double frequency clock from the IOPLL. Regards111Views0likes0CommentsRe: onnecting the F-Tile Reference and System PLL Clock IP out_coreclk_#i port to an IOPLL FPGA IP
Hi, Please help me understand few things. 1) Are you checking the PLL status in HW or in simulation? 2) In the port map, the 'locked' signal is open. How are you checking the status of the PLL. 3) What is the status of rst input port to the PLL? The frequency of the output clock from PLL is valid only after it gets locked. You should be measuring it only after lock. Regards371Views0likes1CommentRe: CAUI‑4 reception on Agilex 5 via GTS PHY IP?
Hi, When you say 'One source says PCS is not supported above 17.16 Gbps' in your description, can you point us to the document which mentions this? To answer your question, Can we implement CAUI‑4 reception manually using GTS PHY IP with PCS enabled? Ans -> Yes Is there a soft MAC IP (even licensed) available that supports this 100G aggregation for Agilex 5? Ans. -> There is no IP that supports 100G aggregation. Are there any Quartus 25.1 limitations for this mode we should be aware of? Ans. -> List of current known issues can be found in the following document. Specifically pointing to GTS Ethernet Hard IP related section. 2.1.1.6. Reduced Tx performance on GTS Ethernet FPGA Hard IP for 25GE... Regards244Views0likes0CommentsRe: Agilex 5 CAUI-10, XLAUI, XLPPI Specification supported for 100G Ethernet
Hi, The GTS User guide mentions restrictions related to bonding. 3.10. Bonding Implementation The GTS PMA/FEC Direct PHY IP only supports TX bonding. The IP does not support RX bonding. The IP supports TX bonding of x2, x4, x6, and x8 PMA channels for PMA direct mode and PCS direct mode. Regards227Views0likes0CommentsRe: Agilex 5 FPGA E-Series Premium Development Kit BTS_FMC design DEsigner Platform components
Hi, The xcvr_st_converter and xcvr_conduit_ctrl does not seem to be standard IP. They seems to be just hand written codes added to the Platform Designer. Check their corresponding .v files. Regards649Views0likes0Comments