Ash_R_Intel
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Re: Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered
Hi, I got a chance to discuss this topic with my colleagues. The recommendation is to follow the datasheet specifications. Read the footnotes also. https://docs.altera.com/r/docs/683301/current/agilextm-7-fpgas-and-socs-device-data-sheet-f-series-and-i-series/f-tile-transceiver-performance-specifications If you notice, there are recommendations on AC-coupling of the pins. The footnote 97 suggests that the FGT lines can be driven in unpowered state as well, provided the voltage are within the specified limits. Hope this helps. Regards4Views1like2CommentsRe: Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered
Hi, Specifically for the PCIe application, the F-tile supports the Hot Plug feature. Refer to the following documentation: https://docs.altera.com/r/docs/683140/25.3/f-tile-avalon-streaming-ip-for-pci-express-user-guide/hot-plug I think this is what you were looking for. Regards22Views1like4CommentsRe: Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX)
Yes, you understood it right. As 20G can be achieved only by GXT channels and for the clocking at that speed ATX pll is the preferred choice. Refer section 3.1 PLLs of the same document. Regards34Views1like4CommentsRe: Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX)
Hi, Please follow the guideline in the L- and H-Tile Transceiver PHY User Guide: https://docs.altera.com/r/docs/683621/current/l-and-h-tile-transceiver-phy-user-guide/pma-bonding As I understand you need PMA only bonding of the channels. For this, you will need only one ATX pll clock to be driving all the channels. Another important consideration you have to make, is the channel placements. As you need max 20G, you will need to use the GXT channels. Hope this helps. Regards19Views0likes5CommentsRe: Agilex5での未使用GTS トランシーババンクのパワーダウンにつきまして
Hi, I am referring to following page: 2.2.3.1. Unused PMA Not Planned for Use in the Future For B23A package of A5E043, as 1C and 1B are on the same side, if both the banks are unused, you can still power both of them down (footnote 14 on the above link). Bank 4C can also be powered down, if it is completely unused. Hope this clarifies. Regards76Views0likes0CommentsRe: Critical Warnings Related to Unused Transceiver Channels in Quartus Prime Pro 20.4
Hi, The PRESERVE_UNUSED_XCVR_CHANNEL option should be used if you intend to use the XCVR channels in future. It is required to prevent the channels from degrading over the time. If you do not intend to use the XCVR channels at all in future, then follow the pin connection guidelines as mentioned in the following page: https://www.intel.com/content/www/us/en/docs/programmable/683814/current/transceiver-pins.html Regards139Views0likes0CommentsRe: onnecting the F-Tile Reference and System PLL Clock IP out_coreclk_#i port to an IOPLL FPGA IP
Hi, Could you verify if the port out_systempll_synthlock_i from F-tile system PLL IP gets asserted or not? You could use this port ANDed with your system level reset to generate overall reset to the IOPLL. Is the input clock to the system PLL always available and at the correct frequency? I don't see any problem is generating a double frequency clock from the IOPLL. Regards113Views0likes0Comments