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dncmrc1's avatar
dncmrc1
Icon for New Contributor rankNew Contributor
2 months ago
Solved

Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX)

We are using a Stratix 10 L-Tile/H-Tile Transceiver Native PHY to implement a DisplayPort TX and RX. The transceiver is set as Basic (Enhanced PCS), TX/RX Duplex. The TX PMA is set as Non bonded, wi...
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  • CheepinC_altera's avatar
    CheepinC_altera
    1 month ago

    Hi,

     

    After consulting with our DisplayPort (DP) IP experts, it appears that our DP is currently not operating in bonded mode for multi‑lane support. You may want to explore our DP IP.

     

    Please let me know if you have any questions or concerns. Thank you.

Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
2 months ago

Hi,

Please follow the guideline in the L- and H-Tile Transceiver PHY User Guide: https://docs.altera.com/r/docs/683621/current/l-and-h-tile-transceiver-phy-user-guide/pma-bonding

As I understand you need PMA only bonding of the channels. For this, you will need only one ATX pll clock to be driving all the channels.  

Another important consideration you have to make, is the channel placements. As you need max 20G, you will need to use the GXT channels. 

Hope this helps.

 

Regards

Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
2 months ago

Yes, you understood it right.

As 20G can be achieved only by GXT channels and for the clocking at that speed ATX pll is the preferred choice. Refer section 3.1 PLLs of the same document.

 

Regards