Forum Discussion

BIdro's avatar
BIdro
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

ALTDDIO IP Cyclone V GT

Hi,

I’m using the ALTDDIO intellectual property but I have problems with it.

The ALTDDIO-Input works very well.

The ALTDDIO-Output does not work. I generate a clock, input signals (reset, data_in) but the output of the component is always 0. I check the reset signal. In the simulation it works well.

Can you help me?

Thanks

Bryan

ALTDDIOOUT_inst1 : ALTDDIOOUT -- MY code

PORT map

(

aclr => reset, --signal active high

outclock => clock_200MHz, -- clock

datain_h => d_ram_out_1h, --x”AAAAA”

datain_l => d_ram_out_1l, --x”55555”

dataout => D_RAM(17 downto 0) -- remain x“00000”

);

  • BIdro's avatar
    BIdro
    5 years ago

    Hi,

    I discovered that the ALTDDIO works but I can not monitor its output with Signal-tap.

    Thank you for the support.

    BR

    Bryan

8 Replies

  • JonWay_altera's avatar
    JonWay_altera
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi @BIdro

    1) Confirm in RTL viewer that your block is connected correctly? make sure nothing is synthesized away.

    2) Check if there is any Quartus Warning messages that can give you extra clue.

    3) Confirm the reset is correct. You can try to use an In-System Source and Probe as reset. Then you can manually toggle it. Or you can confirm it in SignalTap.

    4) Confirm the clock is correct. Make sure it is toggling.

    • BIdro's avatar
      BIdro
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi JonWay,

      The name of my component is PROVA2.

      1- Yes, I confirm that the component is connected in the RTL viewer. (see ALTDDIO_1)

      2- The only warning refers to clock (see ALTDDIO_2)

      3-4- Yes, I confirm that clock is toggling. (see ALTDDIO_0)

      I try the reset/aclr at '0', at '1' and to toggle it.

      I'm using Quartus 18.1.

      Thanks

      Bryan