BIdro
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Re: Quad SPI Flash programming with Quartus_hps.exe
Hi Aliff, I'm using Quartus Prime Standard Edition 18.1 and the program "Embedded_Command_Shell" belongs to the version 16 of the Quartus. I'm using the Cyclone V SE 5CSEMA5F31I7N on a custom board. The QSPI is connected to the qspi controller of the HPS. The layout is good (lenght match, impedance). I tested it with oscilloscope. The frequency of the QSPI clock generated is 781.25 KHz. Thanks, Bryan2.2KViews0likes0CommentsQuad SPI Flash programming with Quartus_hps.exe
Hi, I need to program a QSPI MICRON NOR FLASH (MT25QL512ABB) connected to the pins of the FPGA QSPI controller (5CSEMA5F31I7N). The program to be saved is the boot file for HPS. I use the tool Embedded_Command_Shell and I run the command $Quartus_hps.exe -c 1 -o PV -a 0xA0000 "file_to program". BSEL[2:0] pins are "111" -> Flash device = 3.3 V Quad SPI flash memory CSEL[1:0] pins are "11" -> HPS1_CLK = 25 MHz In the platform designer project I created HPS instance and in "HPS Clocks" menu I have: QSPI clock source: Peripheral QSPI CLOCK QSPI clock frequency: 50 MHz When I run the command to program and verify, the clock generated is 781 KHz and the verify always fails at different times. I expected the QSPI clock to be 50 MHz, but not that low. Some advice? Thanks, BryanSolved2.3KViews0likes8CommentsRe: Ethernet RGMII Cyclone V
Hi, Yes, the signal input "eth_tse_0_mac_rgmii_connection_rgmii_in" of the HPS is connected directly to the input ports of the top_level. I saw the project from Rocketboards but the 2 ethernet peripherals are connected to the HPS. Instead I need 1 ethernet peripheral to be controlled by NIOS processor in RGMII configuration. Thanks, Bryan2.1KViews0likes0CommentsEthernet RGMII Cyclone V
Hi, I'm trying to implement an ethernet application in RGMII mode with a NIOS processor in a Cyclone V 5CSEMA5F31 FPGA and Quartus Prime standard Edition 18.1. I followed a tutorial for Triple-Speed_Ethernet IP and I instantiated the following components in QSYS: - NIOS II Processor - CLOCK NIOS - On-Chip Memory (NIOS - TSE) - Triple-Speed Ethernet Intel FPGA IP (RGMII) - Scatter-Gather DMA Controller RX - Scatter-Gather DMA Controller TX - On-Chip Memory Intel FPGA IP (descriptor memory for sgdma) I created the Soc_system with the QSYS and I connected input and output to the respective ports. This error occurred during the Analysis&Synthesis : Error (15871): Input port DATAIN of DDIO_IN primitive "soc_system:comp_SoC_System|soc_system_eth_tse_0:eth_tse_0|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in1:the_rgmii_in1|altddio_in:altddio_in_component|ddio_in_gsd:auto_generated|ddio_ina[0]" must come from an I/O IBUF or DELAY_CHAIN primitive I tried to use an ALTIOBUF component for the input bus RGMII_RX(3 downto 0) but it does not work. Can you help me? Thanks BryanSolved2.2KViews0likes7Commentscritical warning with SDI II IP instance
Hi, I'm using Cyclone V GT and the SDI II IP. When I run the Analysis and Sinthesys, a critical warning occurs: "Critical Warning (184043): Fitter was unable to find Transceiver Reconfiguration Controllers associated with the following 2 transceiver PHY IP component blocks" How can I solve this problem? Thanks, Bryan386Views0likes0Comments