Ethernet RGMII Cyclone V

Hi,

I'm trying to implement an ethernet application in RGMII mode with a NIOS processor in a Cyclone V 5CSEMA5F31 FPGA and Quartus Prime standard Edition 18.1.

I followed a tutorial for Triple-Speed_Ethernet IP and I instantiated the following components in QSYS:

- NIOS II Processor

- CLOCK NIOS

- On-Chip Memory (NIOS - TSE)

- Triple-Speed Ethernet Intel FPGA IP (RGMII)

- Scatter-Gather DMA Controller RX

- Scatter-Gather DMA Controller TX

- On-Chip Memory Intel FPGA IP (descriptor memory for sgdma)

I created the Soc_system with the QSYS and I connected input and output to the respective ports.

This error occurred during the Analysis&Synthesis :

Error (15871): Input port DATAIN of DDIO_IN primitive "soc_system:comp_SoC_System|soc_system_eth_tse_0:eth_tse_0|altera_eth_tse_mac:i_tse_mac|altera_tse_rgmii_module:U_RGMII|altera_tse_rgmii_in1:the_rgmii_in1|altddio_in:altddio_in_component|ddio_in_gsd:auto_generated|ddio_ina[0]" must come from an I/O IBUF or DELAY_CHAIN primitive

I tried to use an ALTIOBUF component for the input bus RGMII_RX(3 downto 0) but it does not work.

Can you help me?

Thanks

Bryan