Forum Discussion
Occasional ContributorALTDDIO IP Cyclone V GT
Hi,
I discovered that the ALTDDIO works but I can not monitor its output with Signal-tap.
Thank you for the support.
BR
Bryan
Occasional ContributorHi JonWay,
The name of my component is PROVA2.
1- Yes, I confirm that the component is connected in the RTL viewer. (see ALTDDIO_1)
2- The only warning refers to clock (see ALTDDIO_2)
3-4- Yes, I confirm that clock is toggling. (see ALTDDIO_0)
I try the reset/aclr at '0', at '1' and to toggle it.
I'm using Quartus 18.1.
Thanks
Bryan
Frequent ContributorI believe you can get rid of that warning by constraining your clocks. See similar case: https://community.intel.com/t5/Intel-Quartus-Prime-Software/CLOCK-50-was-determined-to-be-clock-but-was-found-without-an/td-p/261272
As for the signaltap, are you using the outclock as your STP clock? Im not sure if the STP not capturing the output, but the fact is it is toggling on the output pin...you might want to confirm with a scope.
If it is really not toggling on the output pin, you might want to reduce the design to a width of 2 and check if this works. I see that your input and output bit width are not the same. I expected that your data_l and data_h and your dataout bus width is the same.
- BIdro
I used as STP clock the ALTDDIO's outclock and another 200 MHz frequency clock. I reduced the width at 2. I put the output signals in 2 test-points to measure with ocilloscope. The result is that in Signal Tap test-points remain '0' and I measure 0 Volt with oscilloscope.
Thanks for the help.
Bryan
- JonWay_altera
To rule out if this is hardware issue, can you try the simple design on a Cyclone V development kit?
- BIdro
Hi,
I try to use the IP in the evaluation board DE1-SoC board (http://de1-soc.terasic.com).
The IP output pins remain at '0' like in the other board when I started.
Is it possible that there is a version problem? I'm using Quartus 18.1 standard edition.
Thanks.
Bryan
