ALT2GXB Help................

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If possible I want to check the actual rate of the transceiver...

Features like eye diagram...bit error rate....

How we can do............

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The rate of your transceiver depends on how you configure it. If you configure it for 5000Mbps, and the transmit and receive PLLs are locked, and the link transfers valid data, then, assuming your references are precise, the 'actual rate' is 5000Mbps.

The eye diagram can be analyzed using the eyeQ feature of the transceiver; this feature is available with the Stratix IV devices, I'm not sure about the Stratix II GX.

The bit-error rate can be tested using a pseudo-random binary sequence (PRBS). A PRBS is a sequence of bits with properties that are a good stress-test of a serial link. When a PRBS pattern is received it can be used as the seed for a receiver-side PRBS generator. Once the receive side PRBS is initialized, the transmitter and receiver PRBS data can be XORed together. If the patterns match, then the result of the XOR is zero, whereas if there are bit-errors, bits will be set. If you count the number of bits set over a long period of time, you create a bit-error-rate tester.

Cheers,

Dave

Thank you Sir....for the nice reply.....

:):)Good news is I am receiving the correct data now what i have transmitted,,,,,,Earlier the TX_CTRLENABLE

was not asserted,after asserting I am getting correct rxdata,before which the reset sequence for both TX & RX were completed:):)

I am sending 16bits per cycle as input to the parallel data to transceiver....and receiving the correct data.........

Right now What I did was I set a counter whose output is connected to the parallel data section of Transmitter...

But I want to enhance this project using some other IP's.....

The thing is I want to transfer data using serial communication....

I want to have some design which can tranfer data between the PC and the FPGA board,then the Data is tranfered through the FPGA serial link,,,,,,

Again the received data shall be saved in PC only.....here transfer is within only a single PC .....but it can also be extended to other PC too...

I have time only to do communication within a PC......

I want your suggestions please about how Can I proceed further......

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Good news is I am receiving the correct data now what i have transmitted,,,,,,Earlier the TX_CTRLENABLE

was not asserted,after asserting I am getting correct rxdata,before which the reset sequence for both TX & RX were completed

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Great! Now that you have got it working in hardware, go back and get it working in simulation. The simulation will help you 'see' parts of the system that will be difficult to observe using an oscilloscope, or help you compare signals you can capture using SignalTapII.

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The thing is I want to transfer data using serial communication....

I want to have some design which can tranfer data between the PC and the FPGA board,then the Data is tranfered through the FPGA serial link,,,,,,

Again the received data shall be saved in PC only.....here transfer is within only a single PC .....but it can also be extended to other PC too...

I have time only to do communication within a PC......

I want your suggestions please about how Can I proceed further......

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If you want to transfer data from the PC-to-FPGA via the serial link, then you will have to use a protocol that a PC can use. PCIe and 10GbE are a couple of possible options. For example, I use a laptop ExpressCard (PCIe) to communicate with the PCIe-based Stratix IV GX development kit. See the discussion here:

http://www.alteraforum.com/forum/showthread.php?t=29851

If you want to use the serial links between two FPGAs, then you can choice the protocol yourself. Altera has an IP core called SerialLite II that might be appropriate. I haven't looked at it, but plan on checking it out. Let me know if it works out for you.

Cheers,

Dave

I am thinking of using the PCIe feature ....by plugging the PCIe into the motherboard...........

Can i get some reference design for this............

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I am thinking of using the PCIe feature ....by plugging the PCIe into the motherboard...........

Can i get some reference design for this............

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There are examples on the Altera web site, there is an example on the Altera Wiki, and I think there is a webinar on the topic too. If there is a PCIe evaluation board for the Stratix II GX device, then it probably has an example design. You'll have to do a little research.

Cheers,

Dave

Hi....

I am trying to use the PCIe in my design.....

Please tell me how to detect the PCIe while the system is booting....

In the Stratix II GX(EP2GX90FF1508C3) device how to configure the PCIe at the time of the Booting...

Which flash device need to be used....

I am able to find the EPM570 & EP2SGX90 devices in the chain.....

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I am trying to use the PCIe in my design.....

Please tell me how to detect the PCIe while the system is booting....

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The FPGA must be configured in PCIe mode in time for the BIOS to configure the PCIe interface memory windows. For the Stratix IV GX development kit, I usually power-on the host machine and put it into its BIOS page. Turning on the host powers on the development kit in an external PCIe motherboard. I then use another machine to configure the development kit with a PCIe design. I then let the host boot; its BIOS configures the PCIe interface. I can then see the PCIe device from Windows or Linux on the host.

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In the Stratix II GX(EP2GX90FF1508C3) device how to configure the PCIe at the time of the Booting...

Which flash device need to be used....

I am able to find the EPM570 & EP2SGX90 devices in the chain.....

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Generally you want to configure as fast as possible, so if you have parallel output flash connected to the FPGA configuration interface, use that.

If you cannot configure the PCIe interface fast enough, then you might be able to trigger your OS to perform a re-enumeration of the PCI bus. This OS feature is used when hot-swapping PCI devices, so you might have to come up with a scheme of generating a fake hot-swap event for your PCIe board.

I haven't looked into the details of this for PCIe boards. I know it is possible for compactPCI boards and Linux, but its not a mainline kernel feature.

Cheers,

Dave

One more thing about thing about the PCIe,

We have bars present in the PCIe...corresponding to the memory size that depends on the configuration we choose....

I know that this memory resides in the system....

I want to know where exactly this memory is located???

for example if bar0 and bar1 are 1Mb & 2Gb SIZE where exactly they are located...

Dear Sir,

I saw in the document Stratix II GX PCI Express Development Board that is present in the following link

www.altera.com/literature/manual/mnl-s (http://www.altera.com/literature/manual/mnl-s)2gx-pci-express-devkit.pdf

in the fpp configuration section(page 24) we have the figure 2–8. which explains the concept for the pcie configuration, in this we have to select config_mode[1:0] as "00" & dipsw+pgm[2:0] for the configuration file page select - 0,1,2.....

in the same pdf under the max ii cpld configuration controller(page 27) it was told to use the pfl mega function .....

can you please explain me how we can use these in the pcie identification.......

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One more thing about thing about the PCIe,

We have bars present in the PCIe...corresponding to the memory size that depends on the configuration we choose....

I know that this memory resides in the system....

I want to know where exactly this memory is located???

for example if bar0 and bar1 are 1Mb & 2Gb SIZE where exactly they are located...

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There is no 'memory' associated with a BAR. Its more like an address decode region in the memory map of your host PC. When the host PC performs a read or write access, the transactions get targeted at the PCIe board.

Its up to your design to actually return something at those addresses. As a simple test, you could have all reads and writes return a fixed pattern, eg. 0xDEADBEEF, and see if you can read those values. Then you can get fancier and have writes write to the LEDs on the board. The PCIe reference designs include DDR memory interfaces.

Cheers,

Dave