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Good news is I am receiving the correct data now what i have transmitted,,,,,,Earlier the TX_CTRLENABLE
was not asserted,after asserting I am getting correct rxdata,before which the reset sequence for both TX & RX were completed
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Great! Now that you have got it working in hardware, go back and get it working in simulation. The simulation will help you 'see' parts of the system that will be difficult to observe using an oscilloscope, or help you compare signals you can capture using SignalTapII.
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The thing is I want to transfer data using serial communication....
I want to have some design which can tranfer data between the PC and the FPGA board,then the Data is tranfered through the FPGA serial link,,,,,,
Again the received data shall be saved in PC only.....here transfer is within only a single PC .....but it can also be extended to other PC too...
I have time only to do communication within a PC......
I want your suggestions please about how Can I proceed further......
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If you want to transfer data from the PC-to-FPGA via the serial link, then you will have to use a protocol that a PC can use. PCIe and 10GbE are a couple of possible options. For example, I use a laptop ExpressCard (PCIe) to communicate with the PCIe-based Stratix IV GX development kit. See the discussion here:
http://www.alteraforum.com/forum/showthread.php?t=29851 If you want to use the serial links between two FPGAs, then you can choice the protocol yourself. Altera has an IP core called SerialLite II that might be appropriate. I haven't looked at it, but plan on checking it out. Let me know if it works out for you.
Cheers,
Dave
Honored Contributor
