Honored Contributor
Honored ContributorThank you Sir....for the nice reply.....
:):)Good news is I am receiving the correct data now what i have transmitted,,,,,,Earlier the TX_CTRLENABLE was not asserted,after asserting I am getting correct rxdata,before which the reset sequence for both TX & RX were completed:):) I am sending 16bits per cycle as input to the parallel data to transceiver....and receiving the correct data......... Right now What I did was I set a counter whose output is connected to the parallel data section of Transmitter... But I want to enhance this project using some other IP's..... The thing is I want to transfer data using serial communication.... I want to have some design which can tranfer data between the PC and the FPGA board,then the Data is tranfered through the FPGA serial link,,,,,, Again the received data shall be saved in PC only.....here transfer is within only a single PC .....but it can also be extended to other PC too... I have time only to do communication within a PC...... I want your suggestions please about how Can I proceed further......
