Honored Contributor
Honored ContributorDear Sir,
I saw in the document Stratix II GX PCI Express Development Board that is present in the following link www.altera.com/literature/manual/mnl-s (http://www.altera.com/literature/manual/mnl-s)2gx-pci-express-devkit.pdfin the fpp configuration section(page 24) we have the figure 2–8. which explains the concept for the pcie configuration, in this we have to select config_mode[1:0] as "00" & dipsw+pgm[2:0] for the configuration file page select - 0,1,2.....
in the same pdf under the max ii cpld configuration controller(page 27) it was told to use the pfl mega function .....
can you please explain me how we can use these in the pcie identification.......
