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Altera_Forum
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16 years ago

ALT_PLLRECONFIG block busy signal problem

I have implemented ALTPLL_RECONFIG megafunction using an454. I have used 6 mifs, 1 mux, 1 reconfiguration block, 1 reconfigurable pll and a simple state machine.

The problem is whenever I run the code, the busy signal toggles. It stays high for 2 clock cycles and low for one clock cycle. Because of this, I was never able to program the pll.

I am attaching the screenshot in order to make things easier.

I have no idea what the problem maybe. I am waiting for assistance. Thanks.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    25 MHZ. Does it have a upper or lower limit?

    --- Quote End ---

    max 100MHz.

    does your read_param, write_param, reconfig, and write_from_rom being asserted? "Busy" will get asserted if anyone of these pins are toggle high.

    din
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    you are right, after initializing read and write parameters, the "busy" signal went low, producing a suitable output.

    This point is not declared explicitly in the application note, I hope ALTERA stresses this detail in the next coming version of the application note.