Agilex 7 R-tile PCIe Root Port reference design

Hello Everyone,

My design need to have PCIe ep in FPGA so (root port in)host machine can interact with it. It also need to have PCIe RP in FPGA so that, FPGA can interact with PCIe devices attached to FPGA card.

I am using Agilex 7 FPGA for my design needs and I am following documentation for PCIe R tile hard IP.

https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/pcie-r-tile-hard-ip.html#tab-blade-1-1

So far, I have experimented with PCIe endpoint example designs and its working well for me,

I am also able to successfully modify PCIe endpoint based example design to fit into my needs.

Now, I want to experiment with PCIe Root Port design.

First of all, I don’t find any example design around PCIe Root port which I can use as reference. If any such resource is available please share it.

I am able to create a root port IP (Gen5 4x4 - RP/RP/RP/RP)and bring it up on my Platform designer system view. I see bunch of AVMM /AVST/Conduit interfaces (attached screenshots below) for which I don’t find any details in documentation page https://www.intel.com/content/www/us/en/docs/programmable/683501/25-1/about-the-r-tile-streaming-fpga-ip-for.html. So, as of now I don’t know what is purpose and usage of these interfaces.

I need help and guidance on how can I make the root port IP start link training, enumeration and beyond that further interaction with PCIe devices ?

Beyond standard PCIe compliant sequences, once PCIe device is enabled by root port, I would need my root port to generate custom transaction ( Cfg RD/WR and Mem RD/WR )to these PCIe devices, how do I do that?

Thank you.