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Re: JTAG timing violations
I have created another SDC file with "JTAG Signal Constraints" template added. The original SDC already have create_clock -name {altera_reserved_tck} -period 30 [get_ports {altera_reserved_tck}] set_clock_groups -asynchronous -group {altera_reserved_tck} still getting JTAG path violation as aseen in the screenshot. the slack increased to -48.914 as Data Required Time of ~44 was added Vs the last run.Re: JTAG timing violations
I added another SDC file containing JTAG signal Constraints template but I still have JTAG violation the first SDC have create_clock -name {altera_reserved_tck} -period 30 [get_ports {altera_reserved_tck}] set_clock_groups -asynchronous -group {altera_reserved_tck} and the second SDC have JTAG Signal Constraints as generated by steps mentioned above. the slack increased to -48.914 as it added Data required time -44.688 Vs in previous run it was reported as 0.JTAG timing violations
Hello Following are my project details LAST_QUARTUS_VERSION "25.1.0 Pro Edition" DEVICE AGIB027R29A1E2VC "Agilex 7" in SDC file - I have create_clock -name {altera_reserved_tck} -period 30 [get_ports {altera_reserved_tck}] set_clock_groups -asynchronous -group {altera_reserved_tck} I am getting timing violation in JTAG path (n/a domain). Lets ignore IOPLL domain violations for this thread. Attached is the timing compilation results for "n/a" path. I need your help in resolving JTAG timing violations. I tried to refer earlier threads on the "JTAG violations" but its not quite helping so opening this thread. thanksRe: IOPLL related clock constraints
module "custom_mem_bridge_2port_0" definition includes instantiation for dual ported memory as following. altera_syncram altera_syncram_component ( .address_a (address), .address_b (address2), .byteena_a (byteenable), .byteena_b (byteenable2), .clock0 (clk), .clocken0 (ram_clocken0), .data_a (writedata), .data_b (writedata2), .q_a (q_a), .q_b (q_b), .rden_a (read), .rden_b (read2), .wren_a (wren_a), .wren_b (wren_b), .aclr0 (1'b0), .aclr1 (1'b0), .address2_a (1'b1), .address2_b (1'b1), .addressstall_a (1'b0), .addressstall_b (1'b0), .clock1 (1'b1), .clocken1 (1'b1), .clocken2 (1'b1), .clocken3 (1'b1), .eccencbypass (1'b0), .eccencparity (8'b0), .eccstatus (), .sclr (1'b0) ); defparam altera_syncram_component.intended_device_family = "Agilex 7", altera_syncram_component.lpm_type = "altera_syncram", altera_syncram_component.operation_mode = "BIDIR_DUAL_PORT", altera_syncram_component.ram_block_type = "AUTO", altera_syncram_component.byte_size = 8, altera_syncram_component.numwords_a = 1024, altera_syncram_component.numwords_b = 1024, altera_syncram_component.width_a = 64, altera_syncram_component.width_b = 64, altera_syncram_component.widthad_a = 10, altera_syncram_component.widthad_b = 10, altera_syncram_component.width_byteena_a = 8, altera_syncram_component.width_byteena_b = 8, altera_syncram_component.address_reg_b = "CLOCK0", altera_syncram_component.byteena_reg_b = "CLOCK0", altera_syncram_component.indata_reg_b = "CLOCK0", altera_syncram_component.outdata_reg_a = "UNREGISTERED", altera_syncram_component.outdata_aclr_a = "NONE", altera_syncram_component.outdata_sclr_a = "NONE", altera_syncram_component.outdata_reg_b = "UNREGISTERED", altera_syncram_component.outdata_aclr_b = "NONE", altera_syncram_component.outdata_sclr_b = "NONE", altera_syncram_component.clock_enable_input_a = "NORMAL", altera_syncram_component.clock_enable_output_a = "BYPASS", altera_syncram_component.clock_enable_input_b = "NORMAL", altera_syncram_component.clock_enable_output_b = "BYPASS", altera_syncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", altera_syncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", altera_syncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", altera_syncram_component.init_file = INIT_FILE, altera_syncram_component.init_file_layout = "Port_A";Re: IOPLL related clock constraints
I am attaching setup report here. I see most of the violation paths are from RAM block - to AVMM interconnect internal buffer. I need help removing these violations. The "custom_mem_bridge_2port_0" is dual ported memory ip wrapped into some logic which adds fanout as it provides copy of AVMM signals from mentoring purpose only, there is no combination logic here. just additional fanouts to S1 and S2 ports goint into DFF inputs and DFF output are used to get copy of AVMM activities for monitoring purpose.Re: IOPLL related clock constraints
Yes, I still need help. I have removed timing constraints related to IOPLL, I have completed generate programming files step. in Messages tab I don't see any message indicating any timing violations. I see Green Correct symbols without warning triangle next to Plan , Place , Route, Retime and fitter (Finalize) steps. Does this means the design has no timing violations at all? I opened Tasks> Timing analyzer. The setup summary violations numbers I am seeing has not changed even after I change compilation parameters from balanced to best performance. I am really questioning, is this the correct and latest set up summary report? and if it is, how come setup violations remained exactly same despite choosing "best performance" compilation options Vs "balanced" option in previous compilation run? In Timing analyzer console I see warning message - Timing requirements not met info message - Automatically attempting to load the "Design Closure Summary" from the compliation timing reports. To change this behavior, see Timer Analyzer Settings. info message - Not able to find relevant "Design Closure Summary" in compilation timing reports. Either the report was not generated for this snapshot or a timing change has occured since compilation. Once compilation was over I have not changes any timing constraints or any project related files; I have simply clicked on Timing analyzer to review timing reports. I am bit puzzled about the last info message, what does the message mean? does this mean that latest run has no violations and its showing me old timing summary results? if it is correctly showing timing violations from latest run, how come setup violations remained exactly same despite choosing "best performance" compilation options Vs "balanced" option in previous compilation run?Re: IOPLL related clock constraints
Sorry, it is Agilex 7 i series FPGA. Yes i did configure IOPLL ip block parameters in platform designer. it is parameterized to have 50MHz input clock and one output clock at 300MHz. I will remove both lines (as above in original post) from sdc file and re-run compilation. At the end of SOF generation sometime, quatus pops up Timing analyzer Summary window and I see summary of violations. How do I get to details per path violations details?IOPLL related clock constraints
Hello Every one I am struggling with creating clock constraint and need help. I have agilix 10 FPGA design at project level top module I have input "iopll_clk_clk". this input is mapped to clock capable input pin on FPGA and is connected to 50MHz on board clock source. The toplevel module has iopll instantiation as following pcie_ed_iopll_0 iopll_0 ( .refclk (iopll_clk_clk), // input, width = 1, refclk.clk .locked (), // output, width = 1, locked.export .rst (resetip_ninit_done_reset), // input, width = 1, reset.reset .outclk0 (iopll_0_outclk0_clk) // output, width = 1, outclk0.clk ); "iopll_0_outclk0_clk" is supposed to be used as clock input for inner logic only. in Platform designer IOPLL is IP is configured to output only one clock at 300MHz. in the project SDC file I have following constraints #iopll Clock create_clock -period 20 [get_ports iopll_clk_clk] #derive_pll_clocks -create_base_clocks - Tried it but not supported for Agilex 10 create_generated_clock -multiply_by 6 -source [get_ports iopll_clk_clk] -name iopll_0_outclk0 [get_pins iopll_0|iopll_0_outclk0] - this is line 17 Here while compiling the design during fitter stage i see following warning messages. Warning(332174): Ignored filter at intel_rtile_pcie_ed.sdc.terp(17): iopll_0|iopll_0_outclk0 could not be matched with a pin Warning(332049): Ignored create_generated_clock at intel_rtile_pcie_ed.sdc.terp(17): Argument <targets> with value [get_pins {iopll_0|iopll_0_outclk0}] contains zero elements This tells me that the IOPLL clocks are not constrained properly and Quartus wont be able to evaluate clock paths correctly for internally generated 300MHz clock. can you help me in figuring out what am i doing wrong here? How can I correctly constraint that iopll is fed with 50MHz clock and its output is 300MHz clock?
