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Re: Error: dut.p0_hip_status has no associated reset.
My QCP intends to read Hip status interface from dut IP to generate internal signals to let the inner logic know about the status of the PCIe endpoint. I cant share much details as its company IP. both hip ports are conduit. MCDMA settings - usermode Data Movers Only and Interface type AVMM. attaching some screenshotsError: dut.p0_hip_status has no associated reset.
Hello Altera I am using Quartus Prime Pro 25.1.0 build 129 03/26/2025 SC Pro Edition. In my Agiliex 7 Design project, I have Intel R-Tile MCDMA for PCI Express intel_pcie_rtile_mcdma Version 5.3.1 Ip instantiated as "dut". in parameters settings I have enabled to have hip status interface. https://www.intel.com/content/www/us/en/docs/programmable/683821/25-1-1/hard-ip-status-interface.html this interface is connected to a custom design QCP file. The QCP uses "app_clk" and "app_nreset_status" from dut ip as its clk and reset inputs. They go through clock bridge and reset bridge. Clock and reset outputs from these bridges are used internally in custom logic code. In platform designer as I connect "dut.p0_hip_status" and "custom_module.pcie_ep_hip_status_in" ports, I get an error as following "Error: pcie_ed: Interfaces custom_module.pcie_ep_hip_status_in and dut.p0_hip_status must have matching associated resets, but dut.p0_hip_status has no associated reset." This Error does not make sense to me, as dut`s hip status interface and my qcp`s status interface ports shows correct clock and reset association in component instantiation tab; and my custom design uses same clock and reset to its clock and reset bridge inputs. can you please help me to understand what is this error about and how do i resolve it?dut.p0_hip_status has no associated reset.
Hello Altera I am using Quartus Prime Pro 25.1.0 build 129 03/26/2025 SC Pro Edition. In my Agiliex 7 Design project, I have Intel R-Tile MCDMA for PCI Express intel_pcie_rtile_mcdma Version 5.3.1 Ip instantiated as "dut". in parameters settings I have enabled to have hip status interface. this interface is connected to a custom design QCP file. The QCP uses "app_clk" and "app_nreset_status" from dut ip as its clk and reset inputs. THey go through clock bridge and reset bridge. Clock and reser outputs from these bridges are used internally in QCP creation In platform designer as I connect "dut.p0_hip_status" and "custom_module_pcie_ep_hip_status_in" I get an error as following "Error: pcie_ed: Interfaces custom_module_pcie_ep_hip_status_in and dut.p0_hip_status must have matching associated resets, but dut.p0_hip_status has no associated reset." This Error does not make sense to me, as dut`s hip status interface and my qcp`s status interface ports shows correct clock and reset association in component instantiation tab; and my custom design uses same clock and reset to its clock and reset bridge inputs. can you please help me to understand what is this error about and how do i resolve it?Re: Implementing MSI-X in Agilex 7 Rtile MCDAM PCIe based design
Anonymous I am attaching screenshot above. When I select Enable CII interface, it adds p0_user_cii port to my dut module, and the signals shown in signal and interface tab shows interface which is matching with what is described on https://www.intel.com/content/www/us/en/docs/programmable/683501/25-1-1/configuration-intercept-interface.html . The list of signals does not match with information provided on https://www.intel.com/content/www/us/en/docs/programmable/817911/25-1-1/configuration-intercept-interface-cii.html At this point seeing this p0_user_cii port at dut, I am understating that i need to write a custom RTL block that interfaces with this port on dut and intercept transactions going to MSI-X capability offset in Config space but i dont know what is the address at which MSI-X capability is located in PCIe config space. As i mentioned in original post table 71 on https://www.intel.com/content/www/us/en/docs/programmable/683501/25-1-1/configuration-intercept-inte... provides cii interface signal list and its details - after reviewing them I have following questions. pX_cii_wr_o Output Indicates that cii_dout_p0/1 is valid. This signal is asserted only for a configuration write request. there is no mention of "pX_cii_rd_o" signal, can pX_cii_wr_o signal be used to determine read request? if this signal is at logic 0 , does it mean that this is CFG read request? pX_cii_addr_o[9:0] Output The double-word register address in the received TLP header on the CII. is this the address associated with CFW write? how do i know Config space offset at which MSI-X capability is located? So I can compare pX_cii_addr_o along with pX_cii_hdr_first_be_o to check if the CFG access to targeting "MSI-X Enable" or"MSI-X function mask" or not. how do I use CII interface so it ignores all offsets other than MSI-X capability structure relatedImplementing MSI-X in Agilex 7 Rtile MCDAM PCIe based design
I am using Agilex 7 - AGIB027R29A1E2VC FPGA. On Rtile I am using Multi Channel DMA FPGA IP for PCI Express - Data Movers Only. https://www.intel.com/content/www/us/en/docs/programmable/683821/25-1-1/data-mover-only.html My design currently performs H2D and D2H DMAs as I need to. Now I want to send MSI-X interrupt after certain DMA completion and thats where I need help. Specifically "MSI-X Enable" and "MSI-X function mask" related functionality. Other Parts related to implementing MSI-X is clear to me. "MSI-X Enable" and "MSI-X function mask" both can be written by host side driver and the interrupt controller inside PCIe ep device is supposed behave accordingly. Currently I am struggling to figure out how can I get a copy of CFG writes to MSI-X capability structure when CFG WRs are targeting "MSI-X Enable" and "MSI-X function mask"? If I get a copy of such CFG writes than my application layer logic can keep track of latest value written and update MSI-X behavior as intended. https://www.intel.com/content/www/us/en/docs/programmable/683501/25-1-1/msi-x.html mentions that "The R-Tile IP for PCIe provides a Configuration Intercept Interface. User soft logic can monitor this interface to get MSI-X Enable and MSI-X function mask related information." https://www.intel.com/content/www/us/en/docs/programmable/683501/25-1-1/configuration-intercept-interface.html mentions that "The Configuration Intercept Interface (CII) allows the application logic to detect the occurrence of a Configuration (CFG) request on the link and to modify its behavior." is there any example on how CII interface can be used to monitor MSI-X capability structure accesses? https://community.intel.com/t5/FPGA-Wiki/Implementing-MSI-X-for-PCI-Express-in-Altera-FPGA-Devices/ta-p/735678 this link appears to be broken furthermore, table 71 on https://www.intel.com/content/www/us/en/docs/programmable/683501/25-1-1/configuration-intercept-interface.html provides cii interface signal list and its details - after reviewing them I have following questions. pX_cii_wr_o Output Indicates that cii_dout_p0/1 is valid. This signal is asserted only for a configuration write request. there is no mention of "pX_cii_rd_o" signal, can pX_cii_wr_o signal be used to determine read request? if this signal is at logic 0 , does it mean that this is CFG read request? pX_cii_addr_o[9:0] Output The double-word register address in the received TLP header on the CII. is this the address associated with CFW write? how do i know Config space offset at which MSI-X capability is located? So I can compare pX_cii_addr_o along with pX_cii_hdr_first_be_o to check if the CFG access to targeting "MSI-X Enable" or"MSI-X function mask" or not. how do I use CII interface so it ignores all offsets other than MSI-X capability structure relatedAgilex 7 R-tile PCIe Root Port reference design
Hello Everyone, My design need to have PCIe ep in FPGA so (root port in)host machine can interact with it. It also need to have PCIe RP in FPGA so that, FPGA can interact with PCIe devices attached to FPGA card. I am using Agilex 7 FPGA for my design needs and I am following documentation for PCIe R tile hard IP. https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/pcie-r-tile-hard-ip.html#tab-blade-1-1 So far, I have experimented with PCIe endpoint example designs and its working well for me, I am also able to successfully modify PCIe endpoint based example design to fit into my needs. Now, I want to experiment with PCIe Root Port design. First of all, I don’t find any example design around PCIe Root port which I can use as reference. If any such resource is available please share it. I am able to create a root port IP (Gen5 4x4 - RP/RP/RP/RP)and bring it up on my Platform designer system view. I see bunch of AVMM /AVST/Conduit interfaces (attached screenshots below) for which I don’t find any details in documentation page https://www.intel.com/content/www/us/en/docs/programmable/683501/25-1/about-the-r-tile-streaming-fpga-ip-for.html. So, as of now I don’t know what is purpose and usage of these interfaces. I need help and guidance on how can I make the root port IP start link training, enumeration and beyond that further interaction with PCIe devices ? Beyond standard PCIe compliant sequences, once PCIe device is enabled by root port, I would need my root port to generate custom transaction ( Cfg RD/WR and Mem RD/WR )to these PCIe devices, how do I do that? Thank you.
