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UserID4331231
Occasional Contributor
8 months agoJTAG timing violations
Hello Following are my project details LAST_QUARTUS_VERSION "25.1.0 Pro Edition" DEVICE AGIB027R29A1E2VC "Agilex 7" in SDC file - I have create_clock -name {altera_reserved_tck} -perio...
UserID4331231
Occasional Contributor
8 months agoI have created another SDC file with "JTAG Signal Constraints" template added.
The original SDC already have
create_clock -name {altera_reserved_tck} -period 30 [get_ports {altera_reserved_tck}]
set_clock_groups -asynchronous -group {altera_reserved_tck}
still getting JTAG path violation as aseen in the screenshot. the slack increased to -48.914 as Data Required Time of ~44 was added Vs the last run.