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UserID4331231's avatar
UserID4331231
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

Agilex 7 R-tile PCIe Root Port reference design

Hello Everyone, My design need to have PCIe ep in FPGA so (root port in)host machine can interact with it. It also need to have PCIe RP in FPGA so that, FPGA can interact with PCIe devices attached ...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
10 months ago

Hi @UserID4331231 ,

May I know which device that you are targetted ? I-series of M-series ?

If you are using I-series device , you may refer to
https://www.rocketboards.org/foswiki/Documentation/Agilex7PCIeRootPortDesign

If you are using M-series device , you may refer to
https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/m-series/pcie_rp/ug-pcie_rp-agx7m-hbm2e/#required-components

Let me know if there is any further clarification is needed.

Regards,
Wincent

  • UserID4331231's avatar
    UserID4331231
    Icon for Occasional Contributor rankOccasional Contributor
    10 months ago

    I am using Agilex 7 - "AGIB027R29A1E2VC" part. I think this part would be I series. is that correct?