why the output wave is showing blue line in questa-intel FPGA

What does your testbench look like (your input stimuli)?

I am just giving a clock in Questa only, so do I need to design input stimuli also?

as it is comparing constant and counter it is generating a pulse with a required frequency of 20khz. I am getting output from lpm_compare.

I am not much aware of how to design a testbench in Quartus for a block diagram design.

please guide me in designing the same.

Hi,

To perform Questa simulation, you need to have a test bench. You may refer to this https://community.intel.com/t5/Intel-Quartus-Prime-Software/Creating-test-bench-code-on-Quartus-prime/m-p/586458 on creating a test bench.

Next, for VWF simulation,

1. The device family used needs to change to the supported family devices (Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, MAX II, MAX V, Stratix IV), either one will do.
2. Compile the design.
3. Create a new University Program VWF.
4. Set the nodes and run timing simulation.

Then, you should be able to get the output result. By setting the first_project.bdf to top-level entity, from your design, this is the VWF waveform generated I obtained (ss_VWF_waveform).

Thanks.

Best Regards,

Ven Ting

Attached with the screenshot of VWF generated waveform.

I am also getting the same waveform.

But while programming and seeing the waveform in oscilloscope i am getting a pulse of 20khz at output of ageb .

The pin_name1 is also at low here in waveform but in oscilloscope it is also coming correctly.

why here the waveform is at low instead of any pulse?

what may be the error due to which this are not coming?

May I know what is the expected behavior of the output aged and pin_name1?

The error occurred may be due to the error in the design file.

Thanks.

Best Regards,

Ven Ting

Hi,

Expected behaviour of output aged will be 50khz pulse(for my case in oscilloscope i got waveform as attached) and for pin_name1 it should generate same clock in ouput which is 50Mhz (In oscilloscope it is coming sinusoidal of 50khz because of filters ) . Both outputs should be a pulse only, of different frequency.

Hi,

Thanks for attaching the image.

I managed to modify and simulate your design to get the expected output waveform. These are some changes made.

First, I would recommend you to design the project using Verilog HDL or VHDL rather than BDF file as Questa simulation does not support BDF. That's why you can't see the output waveform when the BDF is set as top-level module.

Second, it is better to run the simulation in Questa than in VWF. Because there is a bug when running simulation in VWF, sometimes it does not work. You would require to create a test bench for to run in Questa.

Third, the first_project.v you created was not function as described in the BDF as the LPM used were not functioned correctly.

Here is the test project I created that works similar as your design. It is designed using the Verilog HDL file and attached with a test bench to run simulation in Questa. The design uses LPM IP cores and instantiate them in the top-level module. After compiling, run RTL simulation, you should be able to see the expected output waveform in Questa.

You may check out some useful links here:

Introduction to Intel® FPGA IP Cores - Generating IP Cores

https://www.intel.com/content/www/us/en/docs/programmable/683102/21-3/generating-ip-cores.html

Intel FPGA Integer Arithmetic IP Cores User Guide

https://www.intel.com/content/www/us/en/docs/programmable/683490/20-3/intel-fpga-integer-arithmetic-ip-cores.html

Hope this might help you. Thanks.

Best Regards,

Ven Ting

Attached with the test_project.qar and the screenshot of the output waveform obtained in Questa.

Hi,

May I know any updates from you?

Thanks.

Best Regards,

Ven Ting