why the output wave is showing blue line in questa-intel FPGA

Hi,

Thanks for attaching the image.

I managed to modify and simulate your design to get the expected output waveform. These are some changes made.

First, I would recommend you to design the project using Verilog HDL or VHDL rather than BDF file as Questa simulation does not support BDF. That's why you can't see the output waveform when the BDF is set as top-level module.

Second, it is better to run the simulation in Questa than in VWF. Because there is a bug when running simulation in VWF, sometimes it does not work. You would require to create a test bench for to run in Questa.

Third, the first_project.v you created was not function as described in the BDF as the LPM used were not functioned correctly.

Here is the test project I created that works similar as your design. It is designed using the Verilog HDL file and attached with a test bench to run simulation in Questa. The design uses LPM IP cores and instantiate them in the top-level module. After compiling, run RTL simulation, you should be able to see the expected output waveform in Questa.

You may check out some useful links here:

Introduction to Intel® FPGA IP Cores - Generating IP Cores

https://www.intel.com/content/www/us/en/docs/programmable/683102/21-3/generating-ip-cores.html

Intel FPGA Integer Arithmetic IP Cores User Guide

https://www.intel.com/content/www/us/en/docs/programmable/683490/20-3/intel-fpga-integer-arithmetic-ip-cores.html

Hope this might help you. Thanks.

Best Regards,

Ven Ting