Altera_Forum
Honored Contributor
Honored Contributorwhy the module is synthesized away?
hello,
i got a problem, here is the my code : attachment 1
and part of the top module is below: attachment 2
Forum Discussion
7 Replies
Altera_ForumCheck reset and clock signals into your design, make sure your module is not stuck in to the reset state.
- Altera_Forum
A design entity is removed in synthesis, if no output pin depends directly or indirectly on it's operation or if it has constant output.
Cause the design is incomplete, I'm unable to see, what is the reason here. I guess, that all output data from the said module gets lost in other parts of the design, that are missing in the posted code. But it can be usually determined from synthesis warnings. - Altera_Forum--- Quote Start --- A design entity is removed in synthesis, if no output pin depends directly or indirectly on it's operation or if it has constant output. Cause the design is incomplete, I'm unable to see, what is the reason here. I guess, that all output data from the said module gets lost in other parts of the design, that are missing in the posted code. But it can be usually determined from synthesis warnings. --- Quote End --- I have brief look to your source code. It lookslike that the problem is your address generation. It looks to me that READ_RAM_ADDR is never set to "1" //ram address always@(negedge CLOCK or negedge RESET_X) begin if(!RESET_X) begin READ_RAM_ADDR <=# P_DLY 10'b0; // GPK end else if(READ_RAM_ADDR == 1'b1) begin if(clkcnt == 6'd10) READ_RAM_ADDR <=# P_DLY 10'd1; if(clkcnt == 6'd20) READ_RAM_ADDR <=# P_DLY 10'd2; if(clkcnt == 6'd30) READ_RAM_ADDR <=# P_DLY 10'd3; else READ_RAM_ADDR <=# P_DLY READ_RAM_ADDR; end else READ_RAM_ADDR <=# P_DLY 6'd0; end
- Altera_Forum--- Quote Start --- I have brief look to your source code. It lookslike that the problem is your address generation. It looks to me that READ_RAM_ADDR is never set to "1" else if(READ_RAM_ADDR == 1'b1) begin if(clkcnt == 6'd10) READ_RAM_ADDR <=# P_DLY 10'd1; end --- Quote End --- sorry, i make a mistake, here READ_RAM_ADDR is READ_RAM_ENABLE. but its not the point.thankyou.
- Altera_Forum--- Quote Start --- A design entity is removed in synthesis, if no output pin depends directly or indirectly on it's operation or if it has constant output. Cause the design is incomplete, I'm unable to see, what is the reason here. I guess, that all output data from the said module gets lost in other parts of the design, that are missing in the posted code. But it can be usually determined from synthesis warnings. --- Quote End --- thank you, i think its the point, according to you suggestion, i will check my design and make sure if this is the point of the problem.thanks again.
- Altera_Forum--- Quote Start --- thank you, i think its the point, according to you suggestion, i will check my design and make sure if this is the point of the problem.thanks again. --- Quote End --- Hi, maybe I'm wrong, but I think your clkcnt is the problem: //clkcnt always@(negedge CLOCK or negedge RESET_X) begin if(!RESET_X) begin clkcnt <=# P_DLY 6'd0; end else if(READ_RAM_ENABLE == 1'b1) begin if(clkcnt == 6'd40) clkcnt <=# P_DLY clkcnt + 6'd1; else clkcnt <=# P_DLY clkcnt; end else clkcnt <=# P_DLY 1'b0; end The counter will never count, because after reset the clkcnt is set to "0". Your counter can only count at clkcnt = 40, but you will never reach this value.
- Altera_Forum
thank you, pletz. I have crrect it , it should be
"if(clkcnt <= 6'd40)", my popurse is that,as the signal is enable, "READ_RAM_ENABLE == 1'b1", and when the counter is less than 40, then it will add 1, when it reach to 40, it will be keep the value "40".
