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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

why the module is synthesized away?

hello, i got a problem, here is the my code : attachment 1 and part of the top module is below: attachment 2
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

--- Quote Start ---

I have brief look to your source code. It lookslike that the problem is your address generation. It looks to me that READ_RAM_ADDR is never set to "1"

else if(READ_RAM_ADDR == 1'b1) begin

if(clkcnt == 6'd10)

READ_RAM_ADDR <=# P_DLY 10'd1;

end

--- Quote End ---

sorry, i make a mistake, here READ_RAM_ADDR is READ_RAM_ENABLE.

but its not the point.thankyou.