why the module is synthesized away?

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thank you, i think its the point, according to you suggestion, i will check my design and make sure if this is the point of the problem.thanks again.

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Hi,

maybe I'm wrong, but I think your clkcnt is the problem:

//clkcnt

always@(negedge CLOCK or negedge RESET_X)

begin

if(!RESET_X)

begin

clkcnt <=# P_DLY 6'd0;

end

else if(READ_RAM_ENABLE == 1'b1) begin

if(clkcnt == 6'd40)

clkcnt <=# P_DLY clkcnt + 6'd1;

else

clkcnt <=# P_DLY clkcnt;

end

else

clkcnt <=# P_DLY 1'b0;

end

The counter will never count, because after reset the clkcnt is set to "0".

Your counter can only count at clkcnt = 40, but you will never reach this value.