why the module is synthesized away?

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A design entity is removed in synthesis, if no output pin depends directly or indirectly on it's operation or if it has constant output.

Cause the design is incomplete, I'm unable to see, what is the reason here. I guess, that all output data from the said module gets lost in other parts of the design, that are missing in the posted code. But it can be usually determined from synthesis warnings.

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I have brief look to your source code. It lookslike that the problem is your address generation. It looks to me that READ_RAM_ADDR is never set to "1"

//ram address

always@(negedge CLOCK or negedge RESET_X)

begin

if(!RESET_X)

begin

READ_RAM_ADDR <=# P_DLY 10'b0; // GPK

end

else if(READ_RAM_ADDR == 1'b1) begin

if(clkcnt == 6'd10)

READ_RAM_ADDR <=# P_DLY 10'd1;

if(clkcnt == 6'd20)

READ_RAM_ADDR <=# P_DLY 10'd2;

if(clkcnt == 6'd30)

READ_RAM_ADDR <=# P_DLY 10'd3;

else

READ_RAM_ADDR <=# P_DLY READ_RAM_ADDR;

end

else

READ_RAM_ADDR <=# P_DLY 6'd0;

end