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Altera_Forum
Honored Contributor
Honored Contributorwhy the module is synthesized away?
hello, i got a problem, here is the my code : attachment 1 and part of the top module is below: attachment 2
Altera_ForumHonored Contributor
Honored Contributorthank you, pletz. I have crrect it , it should be
"if(clkcnt <= 6'd40)", my popurse is that,as the signal is enable, "READ_RAM_ENABLE == 1'b1", and when the counter is less than 40, then it will add 1, when it reach to 40, it will be keep the value "40".
