when simulating with modelsim,the question appears!

You question isnt very clear.

For your second question, you can just browse to any design unit and drag/drop the signals you want to see on the wave window

Tricky,

Thanks for your reply. My english is not well,and i am new to modelsim.

The first question:

when i use modelsim to simulation over quartus II,It faild by RTL level simulation.

the error message is below:# ** Error: (vsim-3732) E:/SIN_GNT/simulation/modelsim/SIN_GNT.vht(60): No default binding for component at 'i1'.# (Port 'altera_reserved_tdo' is not on the entity.)# Region: /sin_gnt_vhd_tst/i1# ** Error: (vsim-3732) E:/SIN_GNT/simulation/modelsim/SIN_GNT.vht(60): No default binding for component at 'i1'.# (Port 'altera_reserved_tdi' is not on the entity.)# Region: /sin_gnt_vhd_tst/i1# ** Error: (vsim-3732) E:/SIN_GNT/simulation/modelsim/SIN_GNT.vht(60): No default binding for component at 'i1'.# (Port 'altera_reserved_tck' is not on the entity.)# Region: /sin_gnt_vhd_tst/i1# ** Error: (vsim-3732) E:/SIN_GNT/simulation/modelsim/SIN_GNT.vht(60): No default binding for component at 'i1'.# (Port 'altera_reserved_tms' is not on the entity.)# Region: /sin_gnt_vhd_tst/i1# Loading rtl_work.data_rom(syn)# Error loading design

but it successed by Gate level simulation.I can't understand the reason .

For the other question:

I usually drag/drop the intermidiate signals from the path(workspace->i1) to the wave window.but sometimes i can get the right answer and sometimes not. can you explain is in detail?

What do you mean "the right answer"? you mean it doesnt behave correctly?

Usually thats because there are errors in the code.

it looks like your test bench is using JTAG signals (altera_reserved_tdo, etc) which must be present on the gate level netlist and not in your RTL.

you can try editing the test bench so it doesn't use altera_reserved_tdo, altera_reserved_tdi, altera_reserved_tck, altera_reserved_tms.

HI,

thepancake,

thanks for your reply. I have a try according to your method. I delete these signals(altera_reserved_tdo, altera_reserved_tdi, altera_reserved_tck, altera_reserved_tms).Luckly,the RTL level simulation is passed. but there is no data in the wave window. and the message is below:# ** Error: (vsim-7) Failed to open VHDL file "DATA_ROM.mif" in rb mode.# No such file or directory. (errno = ENOENT)

In this situation, I tried to use gate level simulation again, to my surprise, The simulation also failed.and the error message is below:# ** Error: (vsim-3817) Formal port "altera_reserved_tms" declared in the entity is not in the component.# Time: 0 ps Iteration: 0 Region: /sin_gnt_vhd_tst/i1 File: SIN_GNT.vho# ** Error: (vsim-3817) Formal port "altera_reserved_tck" declared in the entity is not in the component.# Time: 0 ps Iteration: 0 Region: /sin_gnt_vhd_tst/i1 File: SIN_GNT.vho# ** Error: (vsim-3817) Formal port "altera_reserved_tdi" declared in the entity is not in the component.# Time: 0 ps Iteration: 0 Region: /sin_gnt_vhd_tst/i1 File: SIN_GNT.vho

So what i should do next step?

if you are using NativeLink you will want to find that .mif and add it to the window where you added the actual test bench .vhd file. or else you could just copy it to simulation/modelsim and the simulator should be able to find it.

not sure what's up with the 2nd part. you might need a different test bench for RTL and timing simulations since the JTAG ports are showing up on the top level of the gate level simulation.