when simulating with modelsim,the question appears!

HI,

thepancake,

thanks for your reply. I have a try according to your method. I delete these signals(altera_reserved_tdo, altera_reserved_tdi, altera_reserved_tck, altera_reserved_tms).Luckly,the RTL level simulation is passed. but there is no data in the wave window. and the message is below:# ** Error: (vsim-7) Failed to open VHDL file "DATA_ROM.mif" in rb mode.# No such file or directory. (errno = ENOENT)

In this situation, I tried to use gate level simulation again, to my surprise, The simulation also failed.and the error message is below:# ** Error: (vsim-3817) Formal port "altera_reserved_tms" declared in the entity is not in the component.# Time: 0 ps Iteration: 0 Region: /sin_gnt_vhd_tst/i1 File: SIN_GNT.vho# ** Error: (vsim-3817) Formal port "altera_reserved_tck" declared in the entity is not in the component.# Time: 0 ps Iteration: 0 Region: /sin_gnt_vhd_tst/i1 File: SIN_GNT.vho# ** Error: (vsim-3817) Formal port "altera_reserved_tdi" declared in the entity is not in the component.# Time: 0 ps Iteration: 0 Region: /sin_gnt_vhd_tst/i1 File: SIN_GNT.vho

So what i should do next step?