when simulating with modelsim,the question appears!

Tricky,

Thanks for your reply. My english is not well,and i am new to modelsim.

The first question:

when i use modelsim to simulation over quartus II,It faild by RTL level simulation.

the error message is below:# ** Error: (vsim-3732) E:/SIN_GNT/simulation/modelsim/SIN_GNT.vht(60): No default binding for component at 'i1'.# (Port 'altera_reserved_tdo' is not on the entity.)# Region: /sin_gnt_vhd_tst/i1# ** Error: (vsim-3732) E:/SIN_GNT/simulation/modelsim/SIN_GNT.vht(60): No default binding for component at 'i1'.# (Port 'altera_reserved_tdi' is not on the entity.)# Region: /sin_gnt_vhd_tst/i1# ** Error: (vsim-3732) E:/SIN_GNT/simulation/modelsim/SIN_GNT.vht(60): No default binding for component at 'i1'.# (Port 'altera_reserved_tck' is not on the entity.)# Region: /sin_gnt_vhd_tst/i1# ** Error: (vsim-3732) E:/SIN_GNT/simulation/modelsim/SIN_GNT.vht(60): No default binding for component at 'i1'.# (Port 'altera_reserved_tms' is not on the entity.)# Region: /sin_gnt_vhd_tst/i1# Loading rtl_work.data_rom(syn)# Error loading design

but it successed by Gate level simulation.I can't understand the reason .

For the other question:

I usually drag/drop the intermidiate signals from the path(workspace->i1) to the wave window.but sometimes i can get the right answer and sometimes not. can you explain is in detail?