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Altera_Forum
Honored Contributor
Honored Contributorwhen simulating with modelsim,the question appears!
hello! when I use modelsim over quartus II to simulation , sometimes It failed by RTL level simulation and successed by gate level simulation simultaneously. maybe the reason is t...
Altera_ForumHonored Contributor
Honored Contributorif you are using NativeLink you will want to find that .mif and add it to the window where you added the actual test bench .vhd file. or else you could just copy it to simulation/modelsim and the simulator should be able to find it.
not sure what's up with the 2nd part. you might need a different test bench for RTL and timing simulations since the JTAG ports are showing up on the top level of the gate level simulation.
