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Altera_Forum
Honored Contributor
Honored Contributorwhen simulating with modelsim,the question appears!
hello! when I use modelsim over quartus II to simulation , sometimes It failed by RTL level simulation and successed by gate level simulation simultaneously. maybe the reason is t...
Altera_ForumHonored Contributor
Honored Contributorit looks like your test bench is using JTAG signals (altera_reserved_tdo, etc) which must be present on the gate level netlist and not in your RTL.
you can try editing the test bench so it doesn't use altera_reserved_tdo, altera_reserved_tdi, altera_reserved_tck, altera_reserved_tms.
