what is the difference between RTL simulation and gate level simulation..

RTL simulation simulates the code directly, so there is no timing information. You do not need to compile the code for RTL simulation. The only languages supported for this are VHDL and Verilog (in modelsim). Because it is just source code, the simulation is pretty quick.

Gate level simulation is a simulation of the compiled netlist. This contains timing information and because it uses compiled code the source can be anything. The problem is that simulation is very very slow.

to stitch together what Tricky said and one of your comments, you will not be able to simulate a schematic in an RTL simulation. you can either code up your schematic as HDL yourself, or go to File > Create/Update > Create HDL for Current File to have Quartus generate HDL from your schematic. you will need to add the generated HDL to your project, remove the schematic from your project, then re-run Analysis and Elaboration before you run Run RTL Simulation

you can also do a post-map netlist simulation with schematic based designs with no timing information. go to Assignments > Settings > EDA Tool Settings > Simulation > More EDA Netlist Writer Settings and check Generate netlist for function simulation only. then you can run Analysis and Synthesis, then EDA Netlist Writer, then run Run Gate Level simulation. the simulation should be faster and not have any of the annoyances of timing simulations

Hi Guys,

I'm having a problem related to what you described as a solution to running RTL simulations for schematics.

I used quartus to generate a file of my schematic, added it to the project and made it top level entity. But, it seems to have mixed up the types. As when I go to simulate I get the following error:

** Failure: (vsim-3807) Types do not match between component and entity for port "oPERIOD_REG".

On further examination, I noticed that the generated file has different types to that specified in my code... the port declararion in my code is:

port

(

iRESET : in STD_LOGIC;

iCLK : in STD_LOGIC;

iRST_DATA_CLK : in STD_LOGIC;

iRST_DATA_IN : in STD_LOGIC;

iRST_DATA_LTCH : in STD_LOGIC;

iRUN_FLAG_CLR : in STD_LOGIC;

--iTX_notRX : in STD_LOGIC; -- default to 0 for RX, if 1 then in TX mode

oPERIOD_REG : out integer range 0 to 16777215;

oPULSE_WIDTH_REG : out integer range 0 to 65535;

oCYCLES_REG : out integer range 0 to 255;

oLATCH_PWM_REGISTERS : out STD_LOGIC;

oRUN_FLAG : out STD_LOGIC

);

but the generated file has used STD_LOGIC_VECTORS instead :

COMPONENT rst_comms

GENERIC (NUM_STAGES : INTEGER

);

PORT(iRESET : IN STD_LOGIC;

iCLK : IN STD_LOGIC;

iRST_DATA_CLK : IN STD_LOGIC;

iRST_DATA_IN : IN STD_LOGIC;

iRST_DATA_LTCH : IN STD_LOGIC;

iRUN_FLAG_CLR : IN STD_LOGIC;

oLATCH_PWM_REGISTERS : OUT STD_LOGIC;

oRUN_FLAG : OUT STD_LOGIC;

oCYCLES_REG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

oPERIOD_REG : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);

oPULSE_WIDTH_REG : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)

);

END COMPONENT;

why would this happen? and what can i do about it?

many thanks

A VHDL novice.

Thank you.

My only concern with using STD_LOGIC_VECTORS was that it would be more complex to do simple mathematical operations such as +1 for counting increments. Since then though I have had a look on that there interweb and discovered that if I use the correct library i should just be able to do it the same way as I do to an integer.

thanks for your help, quick and to the point.

D

yeah, i am just starting to realise that now as I get more into things. Although as a beginner the schematics really help me to visualise what is going on. Much more so than component and port-mapping. Unfortunately schematics do appear to have their limitations.

D