what is the difference between RTL simulation and gate level simulation..

RTL simulation simulates the code directly, so there is no timing information. You do not need to compile the code for RTL simulation. The only languages supported for this are VHDL and Verilog (in modelsim). Because it is just source code, the simulation is pretty quick.

Gate level simulation is a simulation of the compiled netlist. This contains timing information and because it uses compiled code the source can be anything. The problem is that simulation is very very slow.