what is the difference between RTL simulation and gate level simulation..

to stitch together what Tricky said and one of your comments, you will not be able to simulate a schematic in an RTL simulation. you can either code up your schematic as HDL yourself, or go to File > Create/Update > Create HDL for Current File to have Quartus generate HDL from your schematic. you will need to add the generated HDL to your project, remove the schematic from your project, then re-run Analysis and Elaboration before you run Run RTL Simulation

you can also do a post-map netlist simulation with schematic based designs with no timing information. go to Assignments > Settings > EDA Tool Settings > Simulation > More EDA Netlist Writer Settings and check Generate netlist for function simulation only. then you can run Analysis and Synthesis, then EDA Netlist Writer, then run Run Gate Level simulation. the simulation should be faster and not have any of the annoyances of timing simulations