what is the difference between RTL simulation and gate level simulation..

Hi Guys,

I'm having a problem related to what you described as a solution to running RTL simulations for schematics.

I used quartus to generate a file of my schematic, added it to the project and made it top level entity. But, it seems to have mixed up the types. As when I go to simulate I get the following error:

** Failure: (vsim-3807) Types do not match between component and entity for port "oPERIOD_REG".

On further examination, I noticed that the generated file has different types to that specified in my code... the port declararion in my code is:

port

(

iRESET : in STD_LOGIC;

iCLK : in STD_LOGIC;

iRST_DATA_CLK : in STD_LOGIC;

iRST_DATA_IN : in STD_LOGIC;

iRST_DATA_LTCH : in STD_LOGIC;

iRUN_FLAG_CLR : in STD_LOGIC;

--iTX_notRX : in STD_LOGIC; -- default to 0 for RX, if 1 then in TX mode

oPERIOD_REG : out integer range 0 to 16777215;

oPULSE_WIDTH_REG : out integer range 0 to 65535;

oCYCLES_REG : out integer range 0 to 255;

oLATCH_PWM_REGISTERS : out STD_LOGIC;

oRUN_FLAG : out STD_LOGIC

);

but the generated file has used STD_LOGIC_VECTORS instead :

COMPONENT rst_comms

GENERIC (NUM_STAGES : INTEGER

);

PORT(iRESET : IN STD_LOGIC;

iCLK : IN STD_LOGIC;

iRST_DATA_CLK : IN STD_LOGIC;

iRST_DATA_IN : IN STD_LOGIC;

iRST_DATA_LTCH : IN STD_LOGIC;

iRUN_FLAG_CLR : IN STD_LOGIC;

oLATCH_PWM_REGISTERS : OUT STD_LOGIC;

oRUN_FLAG : OUT STD_LOGIC;

oCYCLES_REG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

oPERIOD_REG : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);

oPULSE_WIDTH_REG : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)

);

END COMPONENT;

why would this happen? and what can i do about it?

many thanks

A VHDL novice.