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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

what is the difference between RTL simulation and gate level simulation..

I don't know the difference between RTL simulation and gate level simulation. when i coded program in VHDL, RTL simulation tool is good working, but when i coded program in block diagram, RT...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

yeah, i am just starting to realise that now as I get more into things. Although as a beginner the schematics really help me to visualise what is going on. Much more so than component and port-mapping. Unfortunately schematics do appear to have their limitations.

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