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Altera_Forum
Honored Contributor
Honored Contributorwhat is the difference between RTL simulation and gate level simulation..
I don't know the difference between RTL simulation and gate level simulation. when i coded program in VHDL, RTL simulation tool is good working, but when i coded program in block diagram, RT...
Altera_ForumHonored Contributor
Honored ContributorThe schematics do not allow integer types, so when they generate the ports it generates std_logic and std_logic_vectors only. So unfortunately you need to use std_logic_vectors too. an integer of range 0 to 255 is a 8 bit value.
