What is PCML?

Hi hdjun,

Take a look at this thread:

http://www.alteraforum.com/forum/showthread.php?t=29929

Since the transceiver circuits on FPGAs are designed to interface to many standards, PCML (pseudo current-mode logic) is whatever Altera wants it to mean, and they don't really document it well :)

The thread above has a simplified model of the transmitter (its not the circuit in the first attachment in the thread, look further down).

Cheers,

Dave

--- Quote Start ---

Positive emitter coupled logic is pecl. PCML spells pseudo current mode logic. The term is mentioned in the device handbooks for FPGAs with Gigabit transceivers.

--- Quote End ---

Thank you very much. Obviously therre is a mistake in the "glossary of high-speed terms" on Altera's website. :)

The definition of PCML seems wrong.

--- Quote Start ---

Hi hdjun,

Take a look at this thread:

Since the transceiver circuits on FPGAs are designed to interface to many standards, PCML (pseudo current-mode logic) is whatever Altera wants it to mean, and they don't really document it well :)

The thread above has a simplified model of the transmitter (its not the circuit in the first attachment in the thread, look further down).

Cheers,

Dave

--- Quote End ---

Hi, Dave

Your reply and your post message did a really great help to me! Thank you very much!

Now, throught my simulation on SPICE, I think the equivalent curcuit of PCML transimiter output buffer is not similar to PCML. In fact, when using the terminition, no matter internal or external one, the transimitter output's behavior is more like the output structure of LVDS, which means when the positive pin drive +8mA current while the negetive pin drive -8mA current at the same time. In this equivalent curcuit, the results of Voh and Vol can match with your experiment data.

But I don't know How is equilent curcuit can be implemented in Arria II GX output buffer. In LVDS's structure, there is four bipolar or cmos swithers to change the direction of output current, among the four swithers, there are two of them are near the termination voltage soure. While in PCML, altera says is the internal termination is off, the output of transmitter is tristate with open drain, where are the two swithers near the termination voltage source??

Further more, I want to use the ArriaII GX transimtter as an output to drive the input of one programmable delay chip NB6L295. The input of NB6L295 can be compatible with the 1.5-V CML standard. If the equivalent curcuit we got is correct, the Voh, Vol, and Vcom can meet the demands of NB6L295 and 1.5-V CML standard. But I wonder what is the maxium sink current the transimitter internal termination resisters can bear, for the 1.5-V termination at the the receiver will give a maxium current of about 12mA through the transimitter's termination resistor when the termination voltage is 0.65V at the transimitter neerend.

thank you for help again!!

Hi hdjun,

--- Quote Start ---

Now, throught my simulation on SPICE, I think the equivalent curcuit of PCML transimiter output buffer is not similar to PCML. In fact, when using the terminition, no matter internal or external one, the transimitter output's behavior is more like the output structure of LVDS, which means when the positive pin drive +8mA current while the negetive pin drive -8mA current at the same time. In this equivalent curcuit, the results of Voh and Vol can match with your experiment data.

--- Quote End ---

That's right. That is what the second LTSpice circuit shows.

--- Quote Start ---

Further more, I want to use the ArriaII GX transimtter as an output to drive the input of one programmable delay chip NB6L295. The input of NB6L295 can be compatible with the 1.5-V CML standard. If the equivalent curcuit we got is correct, the Voh, Vol, and Vcom can meet the demands of NB6L295 and 1.5-V CML standard. But I wonder what is the maxium sink current the transimitter internal termination resisters can bear, for the 1.5-V termination at the the receiver will give a maxium current of about 12mA through the transimitter's termination resistor when the termination voltage is 0.65V at the transimitter neerend.

--- Quote End ---

Are you driving a clock-like signal to the delay chip, or a signal that can be spread using a PRBS signal? If so, then you could consider AC-coupling the link, and then it does not matter what the common-mode voltage is, or what the transmitter current capability is. The only thing that will matter is the voltage-swing at the transmitter and receiver.

Cheers,

Dave

--- Quote Start ---

Hi hdjun,

Are you driving a clock-like signal to the delay chip, or a signal that can be spread using a PRBS signal? If so, then you could consider AC-coupling the link, and then it does not matter what the common-mode voltage is, or what the transmitter current capability is. The only thing that will matter is the voltage-swing at the transmitter and receiver.

--- Quote End ---

Hi, Dave

Thank you for your response and your good suggestion!

Because I want to use the voltage level (the more stable part of the high-speed signal) and hope that the voltage level could not drop or rise when the transimitter drive continuantly logic "1" or logic "0" at some time. So I would prefer the DC-couple termination in my design. Consequently, the sink current capability seems important to instructing my design.

Altera's documents say that 1.5-V PCML can be compatible with 1.5-V PCML through DC or AC coupled termination while only compatible with 2.5-V or higher PCML through AC coupled termination. I think maybe it is ok with 1.5-V CML DC-coupled termination, but I am not sure. Maybe, we should choose the AC-coupled termination for safer and less risk, haha.:cool:

--- Quote Start ---

Because I want to use the voltage level (the more stable part of the high-speed signal) and hope that the voltage level could not drop or rise when the transimitter drive continuantly logic "1" or logic "0" at some time. So I would prefer the DC-couple termination in my design. Consequently, the sink current capability seems important to instructing my design.

--- Quote End ---

I have not looked at your clock buffer chip. However, if it has an output enable control, you could always use that to disable the output.

Another method is that you put an external bias resistor on one leg of the AC coupled differential signal, or on both, to hold the differential voltage large enough that when there is no signal, the clock buffer will output either high or low. In fact, read the data sheet for the buffer, some parts have this sort of protection against no-input already built in.

--- Quote Start ---

Altera's documents say that 1.5-V PCML can be compatible with 1.5-V PCML through DC or AC coupled termination while only compatible with 2.5-V or higher PCML through AC coupled termination. I think maybe it is ok with 1.5-V CML DC-coupled termination, but I am not sure. Maybe, we should choose the AC-coupled termination for safer and less risk, haha.:cool:

--- Quote End ---

You could always replace the AC coupling capacitors with 0-Ohm resistors on your prototype boards. That would allow you to test both schemes. You could also add pull-up/downs at the clock inputs to bias the AC coupled links to be stable logic levels when no inputs are toggling. This would allow you to test the various schemes.

If you have the space, route an output from the clock buffer back to a receiver input on the FPGA. This would allow you to send clock signals and PRBS signals through your buffer and back to the FPGA. The received clock/data can then be compared against the transmitted clock/data. If you get errors with the resistor bias network scheme, then you would know not to use it. If both the AC and DC coupled schemes work fine, then you can select the one you like.

Cheers,

Dave

--- Quote Start ---

If you have the space, route an output from the clock buffer back to a receiver input on the FPGA. This would allow you to send clock signals and PRBS signals through your buffer and back to the FPGA. The received clock/data can then be compared against the transmitted clock/data. If you get errors with the resistor bias network scheme, then you would know not to use it. If both the AC and DC coupled schemes work fine, then you can select the one you like.

--- Quote End ---

Hi, Dave

Thank you for your help, I will try these method and then post my results here.

The description can be found in https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/wp/wp_hs_transceiver.pdf

It is a white paper published by Altera in 2002.

Giancarlo