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Altera_Forum
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14 years ago

What is PCML?

Hi, I am confused about the PCML, I think it is a I/O standard like CML(Current Mode Logic), and so I guess PCML means Pseudo Current Mode Logic. But the Glossary in Altera's web sit defi...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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Hi hdjun,

Are you driving a clock-like signal to the delay chip, or a signal that can be spread using a PRBS signal? If so, then you could consider AC-coupling the link, and then it does not matter what the common-mode voltage is, or what the transmitter current capability is. The only thing that will matter is the voltage-swing at the transmitter and receiver.

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Hi, Dave

Thank you for your response and your good suggestion!

Because I want to use the voltage level (the more stable part of the high-speed signal) and hope that the voltage level could not drop or rise when the transimitter drive continuantly logic "1" or logic "0" at some time. So I would prefer the DC-couple termination in my design. Consequently, the sink current capability seems important to instructing my design.

Altera's documents say that 1.5-V PCML can be compatible with 1.5-V PCML through DC or AC coupled termination while only compatible with 2.5-V or higher PCML through AC coupled termination. I think maybe it is ok with 1.5-V CML DC-coupled termination, but I am not sure. Maybe, we should choose the AC-coupled termination for safer and less risk, haha.:cool: