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Because I want to use the voltage level (the more stable part of the high-speed signal) and hope that the voltage level could not drop or rise when the transimitter drive continuantly logic "1" or logic "0" at some time. So I would prefer the DC-couple termination in my design. Consequently, the sink current capability seems important to instructing my design.
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I have not looked at your clock buffer chip. However, if it has an output enable control, you could always use that to disable the output.
Another method is that you put an external bias resistor on one leg of the AC coupled differential signal, or on both, to hold the differential voltage large enough that when there is no signal, the clock buffer will output either high or low. In fact, read the data sheet for the buffer, some parts have this sort of protection against no-input already built in.
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Altera's documents say that 1.5-V PCML can be compatible with 1.5-V PCML through DC or AC coupled termination while only compatible with 2.5-V or higher PCML through AC coupled termination. I think maybe it is ok with 1.5-V CML DC-coupled termination, but I am not sure. Maybe, we should choose the AC-coupled termination for safer and less risk, haha.:cool:
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You could always replace the AC coupling capacitors with 0-Ohm resistors on your prototype boards. That would allow you to test both schemes. You could also add pull-up/downs at the clock inputs to bias the AC coupled links to be stable logic levels when no inputs are toggling. This would allow you to test the various schemes.
If you have the space, route an output from the clock buffer back to a receiver input on the FPGA. This would allow you to send clock signals and PRBS signals through your buffer and back to the FPGA. The received clock/data can then be compared against the transmitted clock/data. If you get errors with the resistor bias network scheme, then you would know not to use it. If both the AC and DC coupled schemes work fine, then you can select the one you like.
Cheers,
Dave
Honored Contributor
