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If you have the space, route an output from the clock buffer back to a receiver input on the FPGA. This would allow you to send clock signals and PRBS signals through your buffer and back to the FPGA. The received clock/data can then be compared against the transmitted clock/data. If you get errors with the resistor bias network scheme, then you would know not to use it. If both the AC and DC coupled schemes work fine, then you can select the one you like.
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Hi, Dave
Thank you for your help, I will try these method and then post my results here.
Honored Contributor
