What is PCML?

Hi hdjun,

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Now, throught my simulation on SPICE, I think the equivalent curcuit of PCML transimiter output buffer is not similar to PCML. In fact, when using the terminition, no matter internal or external one, the transimitter output's behavior is more like the output structure of LVDS, which means when the positive pin drive +8mA current while the negetive pin drive -8mA current at the same time. In this equivalent curcuit, the results of Voh and Vol can match with your experiment data.

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That's right. That is what the second LTSpice circuit shows.

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Further more, I want to use the ArriaII GX transimtter as an output to drive the input of one programmable delay chip NB6L295. The input of NB6L295 can be compatible with the 1.5-V CML standard. If the equivalent curcuit we got is correct, the Voh, Vol, and Vcom can meet the demands of NB6L295 and 1.5-V CML standard. But I wonder what is the maxium sink current the transimitter internal termination resisters can bear, for the 1.5-V termination at the the receiver will give a maxium current of about 12mA through the transimitter's termination resistor when the termination voltage is 0.65V at the transimitter neerend.

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Are you driving a clock-like signal to the delay chip, or a signal that can be spread using a PRBS signal? If so, then you could consider AC-coupling the link, and then it does not matter what the common-mode voltage is, or what the transmitter current capability is. The only thing that will matter is the voltage-swing at the transmitter and receiver.

Cheers,

Dave