What is micro Setup time?

That's the setup and hold you learned in college, i.e. the amount of time before and after the .clk hits a register that the .data must be stable, or else the register could go metastable. They're small numbers dwarfed by the variance in data and clock delays getting to the register. For example, the uTsu of a register might be 150ps. After place and route, the data path to the register might be 1ns longer than the clock path. TimeQuest uses both of these to say your data needs to be available 1.15ns before the clock(at the I/O).

What do mean by " So when we do a setup check on this path, the Data Arrival Path must get to the FPGA before the data required path's micro setup time(utsu)"

Where's that from? That's the technical answer, i.e. your data has to be at the register before the clock by the amount of the uTsu. That's just looking at the register. If you step back and look at data path and clock path, then you're looking at the whole picture, and that is what the Data Arrival Path and Data Required Path cover. (Those terms should be in the handbook or TQ documentation, but running "report_timing -setup ..." on any path in your design and looking at the Data Path tab should help understand Data Arrival and Data Required.)

Hello RySc,

Yes. (At least that's what I mean when I talk about a clock domain...)

And clock crossing means one particular data passing through register [fed by clock a] and another register [fed by clock b]

It important to track the data path clock propagation as well as the clock to out times of the part. The propagation time of the clock to part input helps the setup, whereas propagation time of data path hurts the setup time. This of course assumes that you aren't dealing with a bidirectional data bus. In that case skew on clock will help setup on one end and hurt it on the other end.:D

Basically from a practical aspect the best way to measure discrete setup of a board to understand the aspect inside the FPGA routes. Is to take a scope on a digital PCB and measure with to probes the clock (trigger) at the destination part with respect to the data (other probe). You want the data to arrive prior to the clock edge (setup time). Hence you see if you move your trigger (clock) probe closer to the source part and keep the probe of data at the destination end you will make your setup much worse because the data will arrive later to the clock edge. You therefore can improve setup on a one direction transfer by increasing propagation delay of the clock.

FPGA is similar to clock distribution as a PCB therefore you have the same issues. Most people will try to keep the clock skew down by using a global clock. Fast routes and local/global clocks are used on data that needs low skew as well across a broad spectrum of the part. One can use enables and pipelining to improve timing.