Altera_Forum
Honored Contributor
Honored ContributorWhat is micro Setup time?
Can anyone please explain what "micro setup time [uTsu]" means. Thanks, AA
Forum Discussion
Altera_ForumHonored Contributor
Honored ContributorThat's the setup and hold you learned in college, i.e. the amount of time before and after the .clk hits a register that the .data must be stable, or else the register could go metastable. They're small numbers dwarfed by the variance in data and clock delays getting to the register. For example, the uTsu of a register might be 150ps. After place and route, the data path to the register might be 1ns longer than the clock path. TimeQuest uses both of these to say your data needs to be available 1.15ns before the clock(at the I/O).
HTorkNew Contributor
Continuing on this really old thread.
The is the information I get on setup slack in TimeQuest.
As you can see, micro setup time [uTsu], is added to the data required path, making the setup slack larger, not smaller.
Isn't this in contradiction to what is mentioned above.
Hope for some help to clearify this.
sstrellSuper Contributor
uTsu is the silicon-based setup timing requirement. It is the latest time before the clock edge that the data must arrive. Look in the Waveform tab to see how it is used to designate the data required time. The timing report you've posted shows the latest data must arrive, taking uTsu into account, and based on the clock edge arriving at the destination register. Normally, I see this value as negative since it should be subtracted from when the clock arrives to calculate the required time. I'm not sure why it's positive in the screenshot. Can you post the waveform tab?
#iwork4intel
- HTork
Here is the included Waveform. In the waveform it is written -0.018ns. But as you can see from the small arrow it is added to data required time.
Below follows verilog code, RTL view and Summary of Paths.
The design is compiled for the Cyclone10LP 10CL025YU256I7G.
It is path#1 (d1->d2) that is given in the waveform above and the Setup Slack details.
module Test01 (input clk, output ClockOut, output reg q);
reg d1; /* synthesis preserve */
reg d2; /* synthesis preserve */
assign ClockOut = clk;
always @ ( posedge (clk))
begin
if((q==1'b1)&(d2==1'b1)&(d1==1'b1))
begin
d1<=1'b0;
d2<=1'b0;
q<=1'b0;
end
else
begin
d1 <= 1'b1;
d2 <= d1;
q <= d2 & 1'b1;
end
end
endmodule
