VHDL String to std_logic_vector conversion

Question

I'm trying to add some comments into my Modelsim wave files, and I realized that Modelsim can display a std_logic_vector as a text string. I've looked around for packages but haven't found anything. I haven't written a type conversion before, but this might be a good one to start on.

The idea would be to change a signal to be different text at the start of each test, so that I can more easily zoom in on test cases. This would be especially helpful for helping me remember how test cases work after (sometimes) months of inactivity. Bookmarks just don't cut it.

If someone knows of a better forum on which to place this, please let me know.

altera_forum · Answer

I dont think I really follow what you mean.

I dont think modelsim would be able to parse the wave files with comments in them. std_logic_vector only has 9 states, so it doesnt cover all of the characters. How about just inputting a string type? Or what you could do is create text input files and give them meaningful names.

Even better, write a testbench that using the text file stimulus, that changes the input based on generics or something like that.

the ieee.std_logic_textio package allows you to write std_logic_vectors out to text files via the line type. The line type is just a pointer to a string, and you can access the string that way if you're comfortable de-referencing pointers in VHDL.

altera_forum · Answer

I think I know what chipslinger wants, I have done similar things to send text in  a packet and have  the simulator (the internal simulator in my case) or Signaltap display the std_logic_vector as ASCII.  I wrote a to_std_logic_vector() function  that accepts a string argument and returns a std_logic_vector.  
function to_std_logic_vector( s : string )
	return std_logic_vector 
	is
		variable r : std_logic_vector( s'length * 8 - 1 downto 0) ;
	begin
		for i in 1 to s'high loop
			r(i * 8 - 1 downto (i - 1) * 8) := std_logic_vector( to_unsigned( character'pos(s(i)) , 8 ) ) ;
		end loop ;
		return r ;
	end function ; You may have to reverse the string first depending on your 'endianness likings': 
function reverse( s : string )
	return string 
	is
		variable r : string(s'high downto s'low) ;
	begin
		for i in 1 to s'high loop
			r(s'high + 1 - i) := s(i) ;
		end loop ;
	return r ;
	end function ;

altera_forum · Answer

Yes, I've done the things you mention, and they are very helpful. There are times when looking at the waveforms is the way to go, and it would be great to have some readable signposts to help guide the way.

I've tried creating strings by hand and Modelsim can indeed display them. Try the following:

signal itest_case : std_logic_vector(95 downto 0) := x"416c746572612072756c6573";

With the Modelsim Wave viewer open, go in and change the radix to ascii, and, voila, "Altera rules" comes up in the waveform viewer.

Yes, I can create constants by hand and assign them, but it would be great if someone had already done a type converter.

Thanks.

altera_forum · Answer

using the functions josb has posted, you can easily read strings in from a text file and do this.

But why not just put the string on the wave window? You know you can output text to the console too from your VHDL testbench?

altera_forum · Answer

Thanks. I will give that conversion a shot.

I'd like to hear about what you mean by displaying simulator text on the wave screen. I often dump text to the console or to a file, but I'm afraid I don't know how to put text on the wave.

Thanks.

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VHDL String to std_logic_vector conversion

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