VHDL String to std_logic_vector conversion

I dont think I really follow what you mean.

I dont think modelsim would be able to parse the wave files with comments in them. std_logic_vector only has 9 states, so it doesnt cover all of the characters. How about just inputting a string type? Or what you could do is create text input files and give them meaningful names.

Even better, write a testbench that using the text file stimulus, that changes the input based on generics or something like that.

the ieee.std_logic_textio package allows you to write std_logic_vectors out to text files via the line type. The line type is just a pointer to a string, and you can access the string that way if you're comfortable de-referencing pointers in VHDL.