VHDL String to std_logic_vector conversion

I think I know what chipslinger wants, I have done similar things to send text in a packet and have the simulator (the internal simulator in my case) or Signaltap display the std_logic_vector as ASCII.

function to_std_logic_vector( s : string )
	return std_logic_vector 
	is
		variable r : std_logic_vector( s'length * 8 - 1 downto 0) ;
	begin
		for i in 1 to s'high loop
			r(i * 8 - 1 downto (i - 1) * 8) := std_logic_vector( to_unsigned( character'pos(s(i)) , 8 ) ) ;
		end loop ;
		return r ;
	end function ;

function reverse( s : string )
	return string 
	is
		variable r : string(s'high downto s'low) ;
	begin
		for i in 1 to s'high loop
			r(s'high + 1 - i) := s(i) ;
		end loop ;
	return r ;
	end function ;