VHDL String to std_logic_vector conversion

Yes, I've done the things you mention, and they are very helpful. There are times when looking at the waveforms is the way to go, and it would be great to have some readable signposts to help guide the way.

I've tried creating strings by hand and Modelsim can indeed display them. Try the following:

signal itest_case : std_logic_vector(95 downto 0) := x"416c746572612072756c6573";

With the Modelsim Wave viewer open, go in and change the radix to ascii, and, voila, "Altera rules" comes up in the waveform viewer.

Yes, I can create constants by hand and assign them, but it would be great if someone had already done a type converter.

Thanks.