VHDl spi adc example
Hello,
i'm learning about spi with altera max 10 using 24 bit adc..
previously i got few examples from few people of the forum but they are very complex to learn..
also please suggest me any course on vhdl to learn..
please try to help me..
Best regards,
Tex
Hi Tex,
Max 10 ADC are line-in ADC. Usually Modular ADC Core IP is used for that. Check these two links http://gogofpga.blog.fc2.com/blog-entry-182.html and https://www.youtube.com/watch?v=0oO1RFa-4Xk&t=1s
The SPI RTL design example can be found had been shared to you before. Can't find any VHDL one. Btw, the design store example design https://www.intel.com/content/www/us/en/design-example/715016/max-10-serial-peripheral-interface-master-an-485.html I had been tested on DE-10 Standard (Cyclone V) ADC since Max 10 ADC are line-in ADC. Check the attached design folder and STP waveform. The function as below:
Control Register Write: CS high, WR high
Transmit through MOSI: CS high, WR high, addr "10"
Status Register Read: CS high, RD high, addr "01"
Received (MISO) to data_bus: CS high, RD high, addr "11"
Thanks,
Best Regards,
Sheng