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Altera_Forum
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Honored ContributorVHDL integers initialization and FPGAs
I've started coding in VHDL just less than a year ago - unexperienced student warning!
My question is about integer initalization. I own an Altera DE1 board and I've also got some experience with Xilinx Spartan 3. With both deviced I've noticed a strange thing about integers. I must initialize an integer to some value at declaration level (i.e. signal int : integer range bla to blabla := 0; ), because otherwise my program may freeze or some other voodoo might appear. Usually I use integer signals for counters (UART interface for instance). Have you ever encountered this before ? I guess I'm configuring/doing something wrong as I know that initialization at declaration level doesn't (or shouldn't?) affect the program after synthesis.16 Replies
Altera_ForumI see, that the integer signals are also reset asynchronously, after that, their state won't depend on an initializer anyway.
A strange point is defining reversed integer ranges with downto. Apparently, it's not forbidden by the VHDL standard. But I wonder, if it may confuse the compiler. And I don't understand the purpose.- Altera_Forum
Have you simulated this code with a testbench? are you sure you arnt missing the state change parameters somehow and letting the counters freewheel?
The counters will have a larger range in real hardware because they have to be converted to bits. Have you any idea in which state the problem occurs? Do you have the testbench code? - Altera_Forum
have you tried simulating it? are you sure you're not missing the state change conditions somehow and allowing the counter to freewheel?
When these integers get converted for synthesis their range will be greater than you specified to fit the number of bits, and if you overflow it will have to wait longer before hitting the final conditions. Do you have a testbench for this code? - Altera_Forum
So how come my design (say a really simple UART receiver) freezes at some point, but when I initialize those integers at definition level it works fine without any glitches?
Please note that I had problems with other designs where I used integers in this manner (for counting). Maybe the problem is with this "init don't care" mentioned above? Anyhow, I attached the code, in case something's not right with it. - Altera_Forum--- Quote Start --- Any signal that is left uninitialised is given the left most value as an initial value. This is why std_logic starts as 'U'. Similarly for unconstrained integers, if you didnt initialise them to 0 the left most value is -2^31. When constrained, like this: signal int : integer range -10 to 10; It would initialise to -10 in VHDL, but when you synthesise it, it will convert it to 5 bits, and then may initialise it to something else. --- Quote End --- The rule definitely doesn't apply to synthesized VHDL. Unless "init don't care" is specified, all VHDL registered signals are initialized to zero. Because integer is represented by unsigned or signed, it will be also initialized to zero by default. The behaviour is however different in functional simulation, so you would want to use explicite initializers for registered signals, if congruence behaviour of simulation and synthesized code is intended. P.S.: I have to correct my statement. The rule applies also to synthesized integer in Quartus. Sorry for the confusion.
- Altera_Forum
I dont understand what the problem is? is it your misunderstanding of initialisation in VHDL?
Any signal that is left uninitialised is given the left most value as an initial value. This is why std_logic starts as 'U'. Similarly for unconstrained integers, if you didnt initialise them to 0 the left most value is -2^31. When constrained, like this: signal int : integer range -10 to 10; It would initialise to -10 in VHDL, but when you synthesise it, it will convert it to 5 bits, and then may initialise it to something else.
