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Altera_Forum
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15 years ago

VHDL integers initialization and FPGAs

I've started coding in VHDL just less than a year ago - unexperienced student warning! My question is about integer initalization. I own an Altera DE1 board and I've also got some experience wi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Have you simulated this code with a testbench? are you sure you arnt missing the state change parameters somehow and letting the counters freewheel?

The counters will have a larger range in real hardware because they have to be converted to bits. Have you any idea in which state the problem occurs?

Do you have the testbench code?